src/soc/fu/compunits/test/test_shiftrot_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 # XXX bad practice: use of global variables
   5 from soc.fu.shift_rot.test.test_pipe_caller import get_cu_inputs
   6 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
   7
   8 from soc.fu.compunits.compunits import ShiftRotFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10
  11
  12 class ShiftRotTestRunner(TestRunner):
  13     def __init__(self, test_data):
  14         super().__init__(test_data, ShiftRotFunctionUnit, self,
  15                          Function.SHIFT_ROT)
  16
  17     def get_cu_inputs(self, dec2, sim):
  18         """naming (res) must conform to ShiftRotFunctionUnit input regspec
  19         """
  20         res = yield from get_cu_inputs(dec2, sim)
  21         return res
  22
  23     def check_cu_outputs(self, res, dec2, sim, code):
  24         """naming (res) must conform to ShiftRotFunctionUnit output regspec
  25         """
  26
  27         print ("outputs", repr(code), res)
  28
  29         # RT
  30         out_reg_valid = yield dec2.e.write_reg.ok
  31         if out_reg_valid:
  32             write_reg_idx = yield dec2.e.write_reg.data
  33             expected = sim.gpr(write_reg_idx).value
  34             cu_out = res['o']
  35             print(f"expected {expected:x}, actual: {cu_out:x}")
  36             self.assertEqual(expected, cu_out, code)
  37
  38         rc = yield dec2.e.rc.data
  39         op = yield dec2.e.insn_type
  40         cridx_ok = yield dec2.e.write_cr.ok
  41         cridx = yield dec2.e.write_cr.data
  42
  43         print ("check extra output", repr(code), cridx_ok, cridx)
  44
  45         if rc:
  46             self.assertEqual(cridx_ok, 1, code)
  47             self.assertEqual(cridx, 0, code)
  48
  49         # CR (CR0-7)
  50         if cridx_ok:
  51             cr_expected = sim.crl[cridx].get_range().value
  52             cr_actual = res['cr_a']
  53             print ("CR", cridx, cr_expected, cr_actual)
  54             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
  55
  56         # XER.ca
  57         cry_out = yield dec2.e.output_carry
  58         if cry_out:
  59             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  60             xer_ca = res['xer_ca']
  61             real_carry = xer_ca & 0b1 # XXX CO not CO32
  62             self.assertEqual(expected_carry, real_carry, code)
  63             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  64             real_carry32 = bool(xer_ca & 0b10) # XXX CO32
  65             self.assertEqual(expected_carry32, real_carry32, code)
  66
  67
  68 if __name__ == "__main__":
  69     unittest.main(exit=False)
  70     suite = unittest.TestSuite()
  71     suite.addTest(ShiftRotTestRunner(ShiftRotTestCase.test_data))
  72
  73     runner = unittest.TextTestRunner()
  74     runner.run(suite)