8cd528de623419c96ef407e4f76154402641c009
2 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
4 from soc
.fu
.spr
.test
.test_pipe_caller
import get_cu_inputs
5 from soc
.fu
.spr
.test
.test_pipe_caller
import SPRTestCase
# creates the tests
7 from soc
.fu
.test
.common
import ALUHelpers
8 from soc
.fu
.compunits
.compunits
import SPRFunctionUnit
9 from soc
.fu
.compunits
.test
.test_compunit
import TestRunner
12 class SPRTestRunner(TestRunner
):
13 def __init__(self
, test_data
):
14 super().__init
__(test_data
, SPRFunctionUnit
, self
,
17 def get_cu_inputs(self
, dec2
, sim
):
18 """naming (res) must conform to SPRFunctionUnit input regspec
20 res
= yield from get_cu_inputs(dec2
, sim
)
23 def check_cu_outputs(self
, res
, dec2
, sim
, code
):
24 """naming (res) must conform to SPRFunctionUnit output regspec
27 rc
= yield dec2
.e
.rc
.data
28 op
= yield dec2
.e
.insn_type
29 cridx_ok
= yield dec2
.e
.write_cr
.ok
30 cridx
= yield dec2
.e
.write_cr
.data
32 print ("check extra output", repr(code
), cridx_ok
, cridx
)
35 self
.assertEqual(cridx_ok
, 1, code
)
36 self
.assertEqual(cridx
, 0, code
)
40 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
41 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
42 yield from ALUHelpers
.get_sim_xer_ov(sim_o
, sim
, dec2
)
43 yield from ALUHelpers
.get_wr_sim_xer_ca(sim_o
, sim
, dec2
)
44 yield from ALUHelpers
.get_wr_fast_spr1(sim_o
, sim
, dec2
)
45 yield from ALUHelpers
.get_wr_slow_spr1(sim_o
, sim
, dec2
)
47 ALUHelpers
.check_xer_ov(self
, res
, sim_o
, code
)
48 ALUHelpers
.check_xer_ca(self
, res
, sim_o
, code
)
49 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
50 ALUHelpers
.check_fast_spr1(self
, res
, sim_o
, code
)
51 ALUHelpers
.check_slow_spr1(self
, res
, sim_o
, code
)
52 ALUHelpers
.check_xer_so(self
, res
, sim_o
, code
)
55 if __name__
== "__main__":
56 unittest
.main(exit
=False)
57 suite
= unittest
.TestSuite()
58 suite
.addTest(SPRTestRunner(SPRTestCase
.test_data
))
60 runner
= unittest
.TextTestRunner()