1 # https://github.com/antonblanchard/microwatt/blob/master/countzero_tb.vhdl
2 from nmigen
import Module
, Signal
3 from nmigen
.cli
import rtlil
4 from nmigen
.back
.pysim
import Simulator
, Delay
5 from nmigen
.test
.utils
import FHDLTestCase
7 from soc
.countzero
.countzero
import ZeroCounter
10 class ZeroCounterTestCase(FHDLTestCase
):
11 def test_zerocounter(self
):
14 m
.submodules
.dut
= dut
= ZeroCounter()
20 print("test zero input")
22 yield dut
.is_32bit_i
.eq(0)
23 yield dut
.count_right_i
.eq(0)
25 result
= yield dut
.result_o
27 # report "bad cntlzd 0 = " & to_hstring(result);
28 assert(result
== 0x40)
29 yield dut
.count_right_i
.eq(1)
31 result
= yield dut
.result_o
32 # report "bad cntlzd 0 = " & to_hstring(result);
33 assert(result
== 0x40)
34 yield dut
.is_32bit_i
.eq(1)
35 yield dut
.count_right_i
.eq(0)
37 result
= yield dut
.result_o
38 # report "bad cntlzw 0 = " & to_hstring(result);
39 assert(result
== 0x20)
40 yield dut
.count_right_i
.eq(1)
42 result
= yield dut
.result_o
43 # report "bad cntlzw 0 = " & to_hstring(result);
44 assert(result
== 0x20)
47 yield dut
.rs_i
.eq(0b00010000)
48 yield dut
.is_32bit_i
.eq(0)
49 yield dut
.count_right_i
.eq(0)
51 result
= yield dut
.result_o
52 assert result
== 4, "result %d" % result
54 yield dut
.count_right_i
.eq(1)
56 result
= yield dut
.result_o
57 assert result
== 59, "result %d" % result
59 yield dut
.is_32bit_i
.eq(1)
61 result
= yield dut
.result_o
62 assert result
== 27, "result %d" % result
64 yield dut
.rs_i
.eq(0b1100000100000000)
65 yield dut
.is_32bit_i
.eq(0)
66 yield dut
.count_right_i
.eq(0)
68 result
= yield dut
.result_o
69 assert result
== 14, "result %d" % result
71 yield dut
.count_right_i
.eq(1)
73 result
= yield dut
.result_o
74 assert result
== 55, "result %d" % result
76 yield dut
.is_32bit_i
.eq(1)
78 result
= yield dut
.result_o
79 assert result
== 23, "result %d" % result
81 yield dut
.count_right_i
.eq(0)
83 result
= yield dut
.result_o
84 assert result
== 14, "result %d" % result
87 sim
.add_process(process
) # or sim.add_sync_process(process), see below
89 # run test and write vcd
91 with sim
.write_vcd(fn
+".vcd", fn
+".gtkw", traces
=dut
.ports()):
98 if __name__
== "__main__":
101 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
102 with
open("countzero.il", "w") as f
: