d109f81f599c335986ef8a847246796cfa40e996
1 # Proof of correctness for partitioned equal signal combiner
2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
5 * https://bugs.libre-soc.org/show_bug.cgi?id=332
8 from nmigen
import (Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
,
10 from nmigen
.asserts
import Assert
, AnyConst
, Assume
, Cover
11 from nmigen
.test
.utils
import FHDLTestCase
12 from nmigen
.cli
import rtlil
14 from soc
.fu
.cr
.main_stage
import CRMainStage
15 from soc
.fu
.alu
.pipe_data
import ALUPipeSpec
16 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
17 from soc
.decoder
.power_enums
import InternalOp
21 # This defines a module to drive the device under test and assert
22 # properties about its outputs
23 class Driver(Elaboratable
):
28 def elaborate(self
, platform
):
32 rec
= CompALUOpSubset()
34 # Setup random inputs for dut.op
38 comb
+= p
.eq(AnyConst(width
))
40 pspec
= ALUPipeSpec(id_wid
=2, op_wid
=recwidth
)
41 m
.submodules
.dut
= dut
= CRMainStage(pspec
)
49 comb
+= [a
.eq(AnyConst(64)),
52 comb
+= dut
.i
.ctx
.op
.eq(rec
)
54 # Assert that op gets copied from the input to output
55 for rec_sig
in rec
.ports():
57 dut_sig
= getattr(dut
.o
.ctx
.op
, name
)
58 comb
+= Assert(dut_sig
== rec_sig
)
60 # big endian indexing. *sigh*
61 cr_arr
= Array([cr
[31-i
] for i
in range(32)])
62 cr_o_arr
= Array([cr_o
[31-i
] for i
in range(32)])
64 xl_fields
= dut
.fields
.FormXL
65 xfx_fields
= dut
.fields
.FormXFX
66 FXM
= xfx_fields
.FXM
[0:-1]
67 with m
.Switch(rec
.insn_type
):
68 with m
.Case(InternalOp
.OP_MTCRF
):
71 comb
+= Assert(cr_o
[4*i
:4*i
+4] == a
[4*i
:4*i
+4])
72 with m
.Case(InternalOp
.OP_MFCR
):
73 with m
.If(rec
.insn
[20]): # mfocrf
76 comb
+= Assert(o
[4*i
:4*i
+4] == cr
[4*i
:4*i
+4])
78 comb
+= Assert(o
[4*i
:4*i
+4] == 0)
79 with m
.Else(): # mfcrf
80 comb
+= Assert(o
== cr
)
81 with m
.Case(InternalOp
.OP_CROP
):
82 bt
= Signal(xl_fields
.BT
[0:-1].shape(), reset_less
=True)
83 ba
= Signal(xl_fields
.BA
[0:-1].shape(), reset_less
=True)
84 bb
= Signal(xl_fields
.BB
[0:-1].shape(), reset_less
=True)
85 comb
+= bt
.eq(xl_fields
.BT
[0:-1])
86 comb
+= ba
.eq(xl_fields
.BA
[0:-1])
87 comb
+= bb
.eq(xl_fields
.BB
[0:-1])
92 comb
+= bit_a
.eq(cr_arr
[ba
])
93 comb
+= bit_b
.eq(cr_arr
[bb
])
94 comb
+= bit_o
.eq(cr_o_arr
[bt
])
97 comb
+= lut
.eq(rec
.insn
[6:10])
98 with m
.If(lut
== 0b1000):
99 comb
+= Assert(bit_o
== bit_a
& bit_b
)
100 with m
.If(lut
== 0b0100):
101 comb
+= Assert(bit_o
== bit_a
& ~bit_b
)
102 with m
.If(lut
== 0b1001):
103 comb
+= Assert(bit_o
== ~
(bit_a ^ bit_b
))
104 with m
.If(lut
== 0b0111):
105 comb
+= Assert(bit_o
== ~
(bit_a
& bit_b
))
106 with m
.If(lut
== 0b0001):
107 comb
+= Assert(bit_o
== ~
(bit_a | bit_b
))
108 with m
.If(lut
== 0b1110):
109 comb
+= Assert(bit_o
== bit_a | bit_b
)
110 with m
.If(lut
== 0b1101):
111 comb
+= Assert(bit_o
== bit_a | ~bit_b
)
112 with m
.If(lut
== 0b0110):
113 comb
+= Assert(bit_o
== bit_a ^ bit_b
)
118 class CRTestCase(FHDLTestCase
):
119 def test_formal(self
):
121 self
.assertFormal(module
, mode
="bmc", depth
=2)
122 def test_ilang(self
):
124 vl
= rtlil
.convert(dut
, ports
=[])
125 with
open("cr_main_stage.il", "w") as f
:
129 if __name__
== '__main__':