src/soc/fu/cr/main_stage.py

   1 # This stage is intended to do Condition Register instructions
   2 # and output, as well as carry and overflow generation.
   3 # NOTE: with the exception of mtcrf and mfcr, we really should be doing
   4 # the field decoding which
   5 # selects which bits of CR are to be read / written, back in the
   6 # decoder / insn-isue, have both self.i.cr and self.o.cr
   7 # be broken down into 4-bit-wide "registers", with their
   8 # own "Register File" (indexed by bt, ba and bb),
   9 # exactly how INT regs are done (by RA, RB, RS and RT)
  10 # however we are pushed for time so do it as *one* register.
  11
  12 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
  13 from nmutil.pipemodbase import PipeModBase
  14 from soc.fu.cr.pipe_data import CRInputData, CROutputData
  15 from soc.decoder.power_enums import InternalOp
  16
  17 from soc.decoder.power_fields import DecodeFields
  18 from soc.decoder.power_fieldsn import SignalBitRange
  19
  20
  21 class CRMainStage(PipeModBase):
  22     def __init__(self, pspec):
  23         super().__init__(pspec, "main")
  24         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  25         self.fields.create_specs()
  26
  27     def ispec(self):
  28         return CRInputData(self.pspec)
  29
  30     def ospec(self):
  31         return CROutputData(self.pspec)
  32
  33     def elaborate(self, platform):
  34         m = Module()
  35         comb = m.d.comb
  36         op = self.i.ctx.op
  37         xl_fields = self.fields.FormXL
  38         xfx_fields = self.fields.FormXFX
  39         # default: cr_o remains same as cr input unless modified, below
  40         cr_o = Signal.like(self.i.cr)
  41         comb += cr_o.eq(self.i.cr)
  42
  43         ##### prepare inputs / temp #####
  44
  45         # Generate array for cr input so bits can be selected
  46         cr_arr = Array([Signal(name=f"cr_arr_{i}") for i in range(32)])
  47         for i in range(32):
  48             comb += cr_arr[i].eq(self.i.cr[31-i])
  49
  50         # Generate array for cr output so the bit to write to can be
  51         # selected by a signal
  52         cr_out_arr = Array([Signal(name=f"cr_out_{i}") for i in range(32)])
  53         for i in range(32):
  54             comb += cr_o[31-i].eq(cr_out_arr[i])
  55             comb += cr_out_arr[i].eq(cr_arr[i])
  56
  57         # Generate the mask for mtcrf, mtocrf, and mfocrf
  58         # replicate every fxm field in the insn to 4-bit, as a mask
  59         FXM = xfx_fields.FXM[0:-1]
  60         mask = Signal(32, reset_less=True)
  61         comb += mask.eq(Cat(*[Repl(FXM[i], 4) for i in range(8)]))
  62
  63         #################################
  64         ##### main switch statement #####
  65
  66         with m.Switch(op.insn_type):
  67             ##### mcrf #####
  68             with m.Case(InternalOp.OP_MCRF):
  69                 # MCRF copies the 4 bits of crA to crB (for instance
  70                 # copying cr2 to cr1)
  71                 BF = xl_fields.BF[0:-1]   # destination CR
  72                 BFA = xl_fields.BFA[0:-1] # source CR
  73
  74                 for i in range(4):
  75                     comb += cr_out_arr[BF*4 + i].eq(cr_arr[BFA*4 + i])
  76
  77             ##### crand, cror, crnor etc. #####
  78             with m.Case(InternalOp.OP_CROP):
  79                 # crand/cror and friends get decoded to the same opcode, but
  80                 # one of the fields inside the instruction is a 4 bit lookup
  81                 # table. This lookup table gets indexed by bits a and b from
  82                 # the CR to determine what the resulting bit should be.
  83
  84                 # Grab the lookup table for cr_op type instructions
  85                 lut = Array([Signal(name=f"lut{i}") for i in range(4)])
  86                 # There's no field, just have to grab it directly from the insn
  87                 for i in range(4):
  88                     comb += lut[i].eq(self.i.ctx.op.insn[6+i])
  89
  90                 # Get the bit selector fields from the instruction
  91                 BT = xl_fields.BT[0:-1]
  92                 BA = xl_fields.BA[0:-1]
  93                 BB = xl_fields.BB[0:-1]
  94
  95                 # Use the two input bits to look up the result in the LUT
  96                 comb += cr_out_arr[BT].eq(lut[Cat(cr_arr[BB], cr_arr[BA])])
  97
  98             ##### mtcrf #####
  99             with m.Case(InternalOp.OP_MTCRF):
 100                 # mtocrf and mtcrf are essentially identical
 101                 # put input (RA) - mask-selected - into output CR, leave
 102                 # rest of CR alone.
 103                 comb += cr_o.eq((self.i.a[0:32] & mask) | (self.i.cr & ~mask))
 104
 105             ##### mfcr #####
 106             with m.Case(InternalOp.OP_MFCR):
 107                 # Ugh. mtocrf and mtcrf have one random bit differentiating
 108                 # them. This bit is not in any particular field, so this
 109                 # extracts that bit from the instruction
 110                 move_one = Signal(reset_less=True)
 111                 comb += move_one.eq(self.i.ctx.op.insn[20])
 112
 113                 # mfocrf
 114                 with m.If(move_one):
 115                     comb += self.o.o.eq(self.i.cr & mask)
 116                 # mfcrf
 117                 with m.Else():
 118                     comb += self.o.o.eq(self.i.cr)
 119
 120         # output and context
 121         comb += self.o.cr.eq(cr_o)
 122         comb += self.o.ctx.eq(self.i.ctx)
 123
 124         return m