src/soc/fu/cr/pipe_data.py

   1 """
   2 Links:
   3 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
   4 """
   5 from nmigen import Signal, Const, Cat
   6 from ieee754.fpcommon.getop import FPPipeContext
   7 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
   8 from soc.fu.cr.cr_input_record import CompCROpSubset
   9 from soc.decoder.power_decoder2 import Data
  10
  11
  12 class CRInputData(IntegerData):
  13     regspec = [('INT', 'ra', '0:63'),      # 64 bit range
  14                ('INT', 'rb', '0:63'),      # 64 bit range
  15                ('CR', 'full_cr', '0:31'), # 32 bit range
  16                ('CR', 'cr_a', '0:3'),     # 4 bit range
  17                ('CR', 'cr_b', '0:3'),     # 4 bit range
  18                ('CR', 'cr_c', '0:3')]     # 4 bit: for CR_OP partial update
  19     def __init__(self, pspec):
  20         super().__init__(pspec, False)
  21         # convenience
  22         self.a, self.b = self.ra, self.rb
  23
  24
  25 class CROutputData(IntegerData):
  26     regspec = [('INT', 'o', '0:63'),      # RA - 64 bit range
  27                ('CR', 'full_cr', '0:31'), # 32 bit range
  28                ('CR', 'cr_a', '0:3')]     # 4 bit range
  29     def __init__(self, pspec):
  30         super().__init__(pspec, True)
  31         # convenience
  32         self.cr = self.cr_a
  33
  34
  35 class CRPipeSpec(CommonPipeSpec):
  36     regspec = (CRInputData.regspec, CROutputData.regspec)
  37     opsubsetkls = CompCROpSubset