src/soc/fu/cr/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.alu.pipe_data import IntegerData
   4
   5
   6 class CRInputData(IntegerData):
   7     regspec = [('INT', 'a', '0:63'),
   8                ('CR', 'cr', '32')]
   9     def __init__(self, pspec):
  10         super().__init__(pspec)
  11         self.a = Signal(64, reset_less=True) # RA
  12         self.cr = Signal(32, reset_less=True) # CR in
  13
  14     def __iter__(self):
  15         yield from super().__iter__()
  16         yield self.a
  17         yield self.cr
  18
  19     def eq(self, i):
  20         lst = super().eq(i)
  21         return lst + [self.a.eq(i.a),
  22                       self.cr.eq(i.cr)]
  23
  24 class CROutputData(IntegerData):
  25     regspec = [('INT', 'o', '0:63'),
  26                ('CR', 'cr', '32')]
  27     def __init__(self, pspec):
  28         super().__init__(pspec)
  29         self.o = Signal(64, reset_less=True) # RA
  30         self.cr = Signal(32, reset_less=True) # CR in
  31
  32     def __iter__(self):
  33         yield from super().__iter__()
  34         yield self.o
  35         yield self.cr
  36
  37     def eq(self, i):
  38         lst = super().eq(i)
  39         return lst + [self.o.eq(i.o),
  40                       self.cr.eq(i.cr)]