src/soc/fu/cr/pipe_data.py

   1 """
   2 Links:
   3 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
   4 """
   5 from nmigen import Signal, Const, Cat
   6 from ieee754.fpcommon.getop import FPPipeContext
   7 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
   8 from soc.fu.cr.cr_input_record import CompCROpSubset
   9 from soc.decoder.power_decoder2 import Data
  10
  11
  12 class CRInputData(IntegerData):
  13     regspec = [('INT', 'ra', '0:63'),      # 64 bit range
  14                ('INT', 'rb', '0:63'),      # 64 bit range
  15                ('CR', 'full_cr', '0:31'), # 32 bit range
  16                ('CR', 'cr_a', '0:3'),     # 4 bit range
  17                ('CR', 'cr_b', '0:3'),     # 4 bit range
  18                ('CR', 'cr_c', '0:3')]     # 4 bit range
  19     def __init__(self, pspec):
  20         super().__init__(pspec)
  21         self.ra = Signal(64, reset_less=True) # RA
  22         self.rb = Signal(64, reset_less=True) # RB
  23         self.full_cr = Signal(32, reset_less=True) # full CR in
  24         self.cr_a = Signal(4, reset_less=True)
  25         self.cr_b = Signal(4, reset_less=True)
  26         self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update
  27         # convenience
  28         self.a, self.b = self.ra, self.rb
  29
  30     def __iter__(self):
  31         yield from super().__iter__()
  32         yield self.ra
  33         yield self.rb
  34         yield self.full_cr
  35         yield self.cr_a
  36         yield self.cr_b
  37         yield self.cr_c
  38
  39     def eq(self, i):
  40         lst = super().eq(i)
  41         return lst + [self.ra.eq(i.ra),
  42                       self.rb.eq(i.rb),
  43                       self.full_cr.eq(i.full_cr),
  44                       self.cr_a.eq(i.cr_a),
  45                       self.cr_b.eq(i.cr_b),
  46                       self.cr_c.eq(i.cr_c)]
  47
  48
  49 class CROutputData(IntegerData):
  50     regspec = [('INT', 'o', '0:63'),      # 64 bit range
  51                ('CR', 'full_cr', '0:31'), # 32 bit range
  52                ('CR', 'cr_a', '0:3')]     # 4 bit range
  53     def __init__(self, pspec):
  54         super().__init__(pspec)
  55         self.o = Data(64, name="o") # RA
  56         self.full_cr = Data(32, name="full_cr")
  57         self.cr_a = Data(4, name="cr_a")
  58         # convenience
  59         self.cr = self.cr_a
  60
  61     def __iter__(self):
  62         yield from super().__iter__()
  63         yield self.o
  64         yield self.full_cr
  65         yield self.cr_a
  66
  67     def eq(self, i):
  68         lst = super().eq(i)
  69         return lst + [self.o.eq(i.o),
  70                       self.full_cr.eq(i.full_cr),
  71                       self.cr_a.eq(i.cr_a)]
  72
  73
  74 class CRPipeSpec(CommonPipeSpec):
  75     regspec = (CRInputData.regspec, CROutputData.regspec)
  76     opsubsetkls = CompCROpSubset
  77     def rdflags(self, e): # in order of regspec
  78         reg1_ok = e.read_reg1.ok # RA/RC
  79         reg2_ok = e.read_reg2.ok # RB
  80         full_reg = e.read_cr_whole # full CR
  81         cr1_en = e.read_cr1.ok # CR A
  82         cr2_en = e.read_cr2.ok # CR B
  83         cr3_en = e.read_cr3.ok # CR C
  84         return Cat(reg1_ok, reg2_ok, full_reg, cr1_en, cr2_en, cr3_en)