src/soc/fu/cr/pipe_data.py

   1 """
   2 Links:
   3 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
   4 """
   5 from nmigen import Signal, Const, Cat
   6 from ieee754.fpcommon.getop import FPPipeContext
   7 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
   8 from soc.fu.cr.cr_input_record import CompCROpSubset
   9 from soc.decoder.power_decoder2 import Data
  10
  11
  12 class CRInputData(IntegerData):
  13     regspec = [('INT', 'a', '0:63'),      # 64 bit range
  14                ('INT', 'b', '0:63'),      # 6B bit range
  15                ('CR', 'full_cr', '0:31'), # 32 bit range
  16                ('CR', 'cr_a', '0:3'),     # 4 bit range
  17                ('CR', 'cr_b', '0:3'),     # 4 bit range
  18                ('CR', 'cr_c', '0:3')]     # 4 bit range
  19     def __init__(self, pspec):
  20         super().__init__(pspec)
  21         self.a = Signal(64, reset_less=True) # RA
  22         self.b = Signal(64, reset_less=True) # RB
  23         self.full_cr = Signal(32, reset_less=True) # full CR in
  24         self.cr_a = Signal(4, reset_less=True)
  25         self.cr_b = Signal(4, reset_less=True)
  26         self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update
  27
  28     def __iter__(self):
  29         yield from super().__iter__()
  30         yield self.a
  31         yield self.b
  32         yield self.full_cr
  33         yield self.cr_a
  34         yield self.cr_b
  35         yield self.cr_c
  36
  37     def eq(self, i):
  38         lst = super().eq(i)
  39         return lst + [self.a.eq(i.a),
  40                       self.b.eq(i.b),
  41                       self.full_cr.eq(i.full_cr),
  42                       self.cr_a.eq(i.cr_a),
  43                       self.cr_b.eq(i.cr_b),
  44                       self.cr_c.eq(i.cr_c)]
  45
  46
  47 class CROutputData(IntegerData):
  48     regspec = [('INT', 'o', '0:63'),      # 64 bit range
  49                ('CR', 'full_cr', '0:31'), # 32 bit range
  50                ('CR', 'cr', '0:3')]     # 4 bit range
  51     def __init__(self, pspec):
  52         super().__init__(pspec)
  53         self.o = Data(64, name="o") # RA
  54         self.full_cr = Data(32, name="full_cr")
  55         self.cr = Data(4, name="cr")
  56
  57     def __iter__(self):
  58         yield from super().__iter__()
  59         yield self.o
  60         yield self.full_cr
  61         yield self.cr
  62
  63     def eq(self, i):
  64         lst = super().eq(i)
  65         return lst + [self.o.eq(i.o),
  66                       self.full_cr.eq(i.full_cr),
  67                       self.cr.eq(i.cr)]
  68
  69
  70 class CRPipeSpec(CommonPipeSpec):
  71     regspec = (CRInputData.regspec, CROutputData.regspec)
  72     opsubsetkls = CompCROpSubset
  73     def rdflags(self, e): # in order of regspec
  74         reg1_ok = e.read_reg1.ok # RA/RC
  75         reg2_ok = e.read_reg2.ok # RB
  76         full_reg = e.read_cr_whole # full CR
  77         cr1_en = e.read_cr1.ok # CR A
  78         cr2_en = e.read_cr2.ok # CR B
  79         cr3_en = e.read_cr3.ok # CR C
  80         return Cat(reg1_ok, reg2_ok, full_reg, cr1_en, cr2_en, cr3_en)