rename IntegerData to FUBaseData
[soc.git] / src / soc / fu / cr / pipe_data.py
1 """
2 Links:
3 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
4 """
5 from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
6 from soc.fu.cr.cr_input_record import CompCROpSubset
7
8
9 class CRInputData(FUBaseData):
10 regspec = [('INT', 'ra', '0:63'), # 64 bit range
11 ('INT', 'rb', '0:63'), # 64 bit range
12 ('CR', 'full_cr', '0:31'), # 32 bit range
13 ('CR', 'cr_a', '0:3'), # 4 bit range
14 ('CR', 'cr_b', '0:3'), # 4 bit range
15 ('CR', 'cr_c', '0:3')] # 4 bit: for CR_OP partial update
16 def __init__(self, pspec):
17 super().__init__(pspec, False)
18 # convenience
19 self.a, self.b = self.ra, self.rb
20
21
22 class CROutputData(FUBaseData):
23 regspec = [('INT', 'o', '0:63'), # RA - 64 bit range
24 ('CR', 'full_cr', '0:31'), # 32 bit range
25 ('CR', 'cr_a', '0:3')] # 4 bit range
26 def __init__(self, pspec):
27 super().__init__(pspec, True)
28 # convenience
29 self.cr = self.cr_a
30
31
32 class CRPipeSpec(CommonPipeSpec):
33 regspec = (CRInputData.regspec, CROutputData.regspec)
34 opsubsetkls = CompCROpSubset