src/soc/fu/div/pipe_data.py

   1 from nmigen import Signal, Const
   2 from soc.fu.pipe_data import IntegerData
   3 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
   4 from soc.fu.alu.pipe_data import ALUInputData  # TODO: check this
   5 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
   6 from ieee754.div_rem_sqrt_rsqrt.core import (
   7     DivPipeCoreConfig, DivPipeCoreInputData,
   8     DivPipeCoreInterstageData, DivPipeCoreOutputData)
   9
  10
  11 class DivPipeSpec(CommonPipeSpec):
  12     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
  13     opsubsetkls = CompLogicalOpSubset
  14     core_config = DivPipeCoreConfig(
  15         bit_width=64,
  16         fract_width=64,
  17         log2_radix=3,
  18     )
  19
  20
  21 class CoreBaseData(ALUInputData):
  22     def __init__(self, pspec, core_data_class):
  23         super().__init__(pspec)
  24         self.core = core_data_class(pspec.core_config)
  25         self.divisor_neg = Signal(reset_less=True)
  26         self.dividend_neg = Signal(reset_less=True)
  27         self.div_by_zero = Signal(reset_less=True)
  28
  29         # set if an overflow for divide extended instructions is detected
  30         # because `abs_dividend >= abs_divisor` for the appropriate bit width;
  31         # 0 if the instruction is not a divide extended instruction
  32         self.dive_abs_overflow_32 = Signal(reset_less=True)
  33         self.dive_abs_overflow_64 = Signal(reset_less=True)
  34
  35     def __iter__(self):
  36         yield from super().__iter__()
  37         yield from self.core.__iter__(self)
  38         yield self.divisor_neg
  39         yield self.dividend_neg
  40
  41     def eq(self, rhs):
  42         return self.eq_without_core(rhs) + self.core.eq(rhs.core)
  43
  44     def eq_without_core(self, rhs):
  45         return super().eq(rhs) + \
  46             [self.divisor_neg.eq(rhs.divisor_neg),
  47              self.dividend_neg.eq(rhs.dividend_neg)]
  48
  49
  50 class CoreInputData(CoreBaseData):
  51     def __init__(self, pspec):
  52         super().__init__(pspec, DivPipeCoreInputData)
  53
  54
  55 class CoreInterstageData(CoreBaseData):
  56     def __init__(self, pspec):
  57         super().__init__(pspec, DivPipeCoreInterstageData)
  58
  59
  60 class CoreOutputData(CoreBaseData):
  61     def __init__(self, pspec):
  62         super().__init__(pspec, DivPipeCoreOutputData)