src/soc/fu/div/pipeline.py

   1 from nmutil.singlepipe import ControlBase
   2 from nmutil.pipemodbase import PipeModBaseChain
   3 from soc.fu.mul.output_stage import DivMulOutputStage
   4 from soc.fu.div.input_stage import DivMulInputStage
   5 from soc.fu.div.output_stage import DivOutputStage
   6 from soc.fu.div.setup_stage import DivSetupStage
   7 from soc.fu.div.core_stages import (DivCoreSetupStage, DivCoreCalculateStage,
   8                                     DivCoreFinalStage)
   9 from soc.fu.div.pipe_data import DivPipeKindConfigCombPipe
  10
  11
  12 class DivStagesStart(PipeModBaseChain):
  13     def get_chain(self):
  14         alu_input = DivMulInputStage(self.pspec)
  15         div_setup = DivSetupStage(self.pspec)
  16         if isinstance(self.pspec.div_pipe_kind.config,
  17                       DivPipeKindConfigCombPipe):
  18             core_setup = [DivCoreSetupStage(self.pspec)]
  19         else:
  20             core_setup = ()
  21         return [alu_input, div_setup, *core_setup]
  22
  23
  24 class DivStagesMiddle(PipeModBaseChain):
  25     def __init__(self, pspec, stage_start_index, stage_end_index):
  26         assert isinstance(pspec.div_pipe_kind.config,
  27                           DivPipeKindConfigCombPipe),\
  28             "DivStagesMiddle must be used with a DivPipeKindConfigCombPipe"
  29         self.stage_start_index = stage_start_index
  30         self.stage_end_index = stage_end_index
  31         super().__init__(pspec)
  32
  33     def get_chain(self):
  34         stages = []
  35         for index in range(self.stage_start_index, self.stage_end_index):
  36             stages.append(DivCoreCalculateStage(self.pspec, index))
  37         return stages
  38
  39
  40 class DivStagesEnd(PipeModBaseChain):
  41     def get_chain(self):
  42         if isinstance(self.pspec.div_pipe_kind.config,
  43                       DivPipeKindConfigCombPipe):
  44             core_final = [DivCoreFinalStage(self.pspec)]
  45         else:
  46             core_final = ()
  47         div_out = DivOutputStage(self.pspec)
  48         alu_out = DivMulOutputStage(self.pspec)
  49         self.div_out = div_out  # debugging - bug #425
  50         return [*core_final, div_out, alu_out]
  51
  52
  53 class DivBasePipe(ControlBase):
  54     def __init__(self, pspec, compute_steps_per_stage=4):
  55         ControlBase.__init__(self)
  56         self.pspec = pspec
  57         self.pipe_start = DivStagesStart(pspec)
  58         self.pipe_middles = []
  59         if isinstance(self.pspec.div_pipe_kind.config,
  60                       DivPipeKindConfigCombPipe):
  61             compute_steps = pspec.core_config.n_stages
  62             for start in range(0, compute_steps, compute_steps_per_stage):
  63                 end = min(start + compute_steps_per_stage, compute_steps)
  64                 self.pipe_middles.append(DivStagesMiddle(pspec, start, end))
  65         else:
  66             self.pipe_middles.append(
  67                 self.pspec.div_pipe_kind.config.core_stage_class(pspec))
  68         self.pipe_end = DivStagesEnd(pspec)
  69         self._eqs = self.connect([self.pipe_start,
  70                                   *self.pipe_middles,
  71                                   self.pipe_end])
  72
  73     def elaborate(self, platform):
  74         m = ControlBase.elaborate(self, platform)
  75         m.submodules.pipe_start = self.pipe_start
  76         for i in range(len(self.pipe_middles)):
  77             name = f"pipe_middle_{i}"
  78             setattr(m.submodules, name, self.pipe_middles[i])
  79         m.submodules.pipe_end = self.pipe_end
  80         m.d.comb += self._eqs
  81         return m