1 # This stage is the setup stage that converts the inputs
2 # into the values expected by DivPipeCore
4 from nmigen
import (Module
, Signal
, Cat
, Repl
, Mux
, Const
, Array
)
5 from nmutil
.pipemodbase
import PipeModBase
6 from soc
.fu
.div
.pipe_data
import DIVInputData
7 from soc
.fu
.alu
.pipe_data
import ALUOutputData
8 from ieee754
.part
.partsig
import PartitionedSignal
9 from soc
.decoder
.power_enums
import InternalOp
11 from soc
.decoder
.power_fields
import DecodeFields
12 from soc
.decoder
.power_fieldsn
import SignalBitRange
13 from soc
.fu
.div
.pipe_data
import CoreInputData
14 from ieee754
.div_rem_sqrt_rsqrt
.core
import DivPipeCoreOperation
17 class DivSetupStage(PipeModBase
):
18 def __init__(self
, pspec
):
19 super().__init
__(pspec
, "setup_stage")
20 self
.fields
= DecodeFields(SignalBitRange
, [self
.i
.ctx
.op
.insn
])
21 self
.fields
.create_specs()
22 self
.abs_divisor
= Signal(64)
23 self
.abs_dividend
= Signal(64)
26 return DIVInputData(self
.pspec
)
29 return CoreInputData(self
.pspec
)
31 def elaborate(self
, platform
):
34 op
, a
, b
= self
.i
.ctx
.op
, self
.i
.a
, self
.i
.b
36 dividend_neg
= self
.o
.dividend_neg
37 divisor_neg
= self
.o
.divisor_neg
38 dividend_o
= core_o
.dividend
39 divisor_o
= core_o
.divisor_radicand
41 comb
+= core_o
.operation
.eq(int(DivPipeCoreOperation
.UDivRem
))
43 comb
+= dividend_neg
.eq(Mux(op
.is_32bit
, a
[31], a
[63]) & op
.is_signed
)
44 comb
+= divisor_neg
.eq(Mux(op
.is_32bit
, b
[31], b
[63]) & op
.is_signed
)
46 # negation of a 64-bit value produces the same lower 32-bit
47 # result as negation of just the lower 32-bits, so we don't
48 # need to do anything special before negating
49 comb
+= self
.abs_divisor
.eq(Mux(divisor_neg
, -b
, b
))
50 comb
+= self
.abs_dividend
.eq(Mux(dividend_neg
, -a
, a
))
52 comb
+= self
.o
.dive_abs_overflow_64
.eq(
53 (self
.abs_dividend
>= self
.abs_divisor
)
54 & (op
.insn_type
== InternalOp
.OP_DIVE
))
56 comb
+= self
.o
.dive_abs_overflow_32
.eq(
57 (self
.abs_dividend
[0:32] >= self
.abs_divisor
[0:32])
58 & (op
.insn_type
== InternalOp
.OP_DIVE
))
60 with m
.If(op
.is_32bit
):
61 comb
+= divisor_o
.eq(self
.abs_divisor
[0:32])
63 comb
+= divisor_o
.eq(self
.abs_divisor
[0:64])
65 comb
+= self
.o
.div_by_zero
.eq(divisor_o
== 0)
67 ##########################
70 with m
.Switch(op
.insn_type
):
71 with m
.Case(InternalOp
.OP_DIV
, InternalOp
.OP_MOD
):
72 with m
.If(op
.is_32bit
):
73 comb
+= dividend_o
.eq(self
.abs_dividend
[0:32])
75 comb
+= dividend_o
.eq(self
.abs_dividend
[0:64])
76 with m
.Case(InternalOp
.OP_DIVE
):
77 with m
.If(op
.is_32bit
):
78 comb
+= dividend_o
.eq(self
.abs_dividend
[0:32] << 32)
80 comb
+= dividend_o
.eq(self
.abs_dividend
[0:64] << 64)
82 ###### sticky overflow and context, both pass-through #####
84 comb
+= self
.o
.xer_so
.eq(self
.i
.xer_so
)
85 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)
87 # pass through core data
89 comb
+= self
.o
.core
.eq(core_o
)