25dedf8b1052d6a34179c2026af02efe24987f3b
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
, CryIn
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import (TestCase
, ALUHelpers
)
16 from soc
.fu
.div
.pipeline
import DIVBasePipe
17 from soc
.fu
.div
.pipe_data
import DIVPipeSpec
21 def get_cu_inputs(dec2
, sim
):
22 """naming (res) must conform to DIVFunctionUnit input regspec
26 yield from ALUHelpers
.get_sim_int_ra(res
, sim
, dec2
) # RA
27 yield from ALUHelpers
.get_sim_int_rb(res
, sim
, dec2
) # RB
28 yield from ALUHelpers
.get_rd_sim_xer_ca(res
, sim
, dec2
) # XER.ca
29 yield from ALUHelpers
.get_sim_xer_so(res
, sim
, dec2
) # XER.so
31 print ("alu get_cu_inputs", res
)
37 def set_alu_inputs(alu
, dec2
, sim
):
38 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
39 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
40 # and place it into data_i.b
42 inp
= yield from get_cu_inputs(dec2
, sim
)
43 yield from ALUHelpers
.set_int_ra(alu
, dec2
, inp
)
44 yield from ALUHelpers
.set_int_rb(alu
, dec2
, inp
)
46 yield from ALUHelpers
.set_xer_ca(alu
, dec2
, inp
)
47 yield from ALUHelpers
.set_xer_so(alu
, dec2
, inp
)
50 # This test bench is a bit different than is usual. Initially when I
51 # was writing it, I had all of the tests call a function to create a
52 # device under test and simulator, initialize the dut, run the
53 # simulation for ~2 cycles, and assert that the dut output what it
54 # should have. However, this was really slow, since it needed to
55 # create and tear down the dut and simulator for every test case.
57 # Now, instead of doing that, every test case in DIVTestCase puts some
58 # data into the test_data list below, describing the instructions to
59 # be tested and the initial state. Once all the tests have been run,
60 # test_data gets passed to TestRunner which then sets up the DUT and
61 # simulator once, runs all the data through it, and asserts that the
62 # results match the pseudocode sim at every cycle.
64 # By doing this, I've reduced the time it takes to run the test suite
65 # massively. Before, it took around 1 minute on my computer, now it
66 # takes around 3 seconds
69 class DIVTestCase(FHDLTestCase
):
72 def __init__(self
, name
):
73 super().__init
__(name
)
76 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None):
77 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
)
78 self
.test_data
.append(tc
)
80 def test_rand_divw(self
):
81 insns
= ["divw", "divw.", "divwo", "divwo."]
83 choice
= random
.choice(insns
)
84 lst
= [f
"{choice} 3, 1, 2"]
85 initial_regs
= [0] * 32
86 initial_regs
[1] = random
.randint(0, (1<<64)-1)
87 initial_regs
[2] = random
.randint(0, (1<<64)-1)
88 self
.run_tst_program(Program(lst
), initial_regs
)
91 pspec
= DIVPipeSpec(id_wid
=2)
92 alu
= DIVBasePipe(pspec
)
93 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
94 with
open("alu_pipeline.il", "w") as f
:
98 class TestRunner(FHDLTestCase
):
99 def __init__(self
, test_data
):
100 super().__init
__("run_all")
101 self
.test_data
= test_data
106 instruction
= Signal(32)
108 pdecode
= create_pdecode()
110 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
112 pspec
= DIVPipeSpec(id_wid
=2)
113 m
.submodules
.alu
= alu
= DIVBasePipe(pspec
)
115 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
116 comb
+= alu
.p
.valid_i
.eq(1)
117 comb
+= alu
.n
.ready_i
.eq(1)
118 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
123 for test
in self
.test_data
:
125 program
= test
.program
126 self
.subTest(test
.name
)
127 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
,
129 gen
= program
.generate_instructions()
130 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
132 index
= sim
.pc
.CIA
.value
//4
133 while index
< len(instructions
):
134 ins
, code
= instructions
[index
]
136 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
139 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
140 ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
141 ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
142 print ("before: so/ov/32", so
, ov
, ov32
)
144 # ask the decoder to decode this binary data (endian'd)
145 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
146 yield instruction
.eq(ins
) # raw binary instr.
148 fn_unit
= yield pdecode2
.e
.fn_unit
149 self
.assertEqual(fn_unit
, Function
.DIV
.value
)
150 yield from set_alu_inputs(alu
, pdecode2
, sim
)
152 opname
= code
.split(' ')[0]
153 yield from sim
.call(opname
)
154 index
= sim
.pc
.CIA
.value
//4
156 vld
= yield alu
.n
.valid_o
159 vld
= yield alu
.n
.valid_o
162 yield from self
.check_alu_outputs(alu
, pdecode2
, sim
, code
)
164 sim
.add_sync_process(process
)
165 with sim
.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
169 def check_alu_outputs(self
, alu
, dec2
, sim
, code
):
171 rc
= yield dec2
.e
.rc
.data
172 cridx_ok
= yield dec2
.e
.write_cr
.ok
173 cridx
= yield dec2
.e
.write_cr
.data
175 print ("check extra output", repr(code
), cridx_ok
, cridx
)
177 self
.assertEqual(cridx
, 0, code
)
179 oe
= yield dec2
.e
.oe
.oe
180 oe_ok
= yield dec2
.e
.oe
.ok
181 if not oe
or not oe_ok
:
182 # if OE not enabled, XER SO and OV must correspondingly be false
183 so_ok
= yield alu
.n
.data_o
.xer_so
.ok
184 ov_ok
= yield alu
.n
.data_o
.xer_ov
.ok
185 self
.assertEqual(so_ok
, False, code
)
186 self
.assertEqual(ov_ok
, False, code
)
191 yield from ALUHelpers
.get_cr_a(res
, alu
, dec2
)
192 yield from ALUHelpers
.get_xer_ov(res
, alu
, dec2
)
193 yield from ALUHelpers
.get_xer_ca(res
, alu
, dec2
)
194 yield from ALUHelpers
.get_int_o(res
, alu
, dec2
)
195 yield from ALUHelpers
.get_xer_so(res
, alu
, dec2
)
197 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
198 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
199 yield from ALUHelpers
.get_sim_xer_ov(sim_o
, sim
, dec2
)
200 yield from ALUHelpers
.get_wr_sim_xer_ca(sim_o
, sim
, dec2
)
201 yield from ALUHelpers
.get_sim_xer_so(sim_o
, sim
, dec2
)
203 ALUHelpers
.check_cr_a(self
, res
, sim_o
, "CR%d %s" % (cridx
, code
))
204 ALUHelpers
.check_xer_ov(self
, res
, sim_o
, code
)
205 ALUHelpers
.check_xer_ca(self
, res
, sim_o
, code
)
206 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
207 ALUHelpers
.check_xer_so(self
, res
, sim_o
, code
)
210 if __name__
== "__main__":
211 unittest
.main(exit
=False)
212 suite
= unittest
.TestSuite()
213 suite
.addTest(TestRunner(DIVTestCase
.test_data
))
215 runner
= unittest
.TextTestRunner()