dcache.py commit first full tranlation pass, about five percent left
[soc.git] / src / soc / fu / div / test / test_pipe_caller.py
1 import random
2 import unittest
3 from soc.simulator.program import Program
4 from soc.config.endian import bigendian
5
6 from soc.fu.test.common import (TestCase, TestAccumulatorBase, skip_case)
7 from soc.fu.div.pipe_data import DivPipeKind
8
9 from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
10 set_alu_inputs, DivTestHelper)
11
12
13 class DivTestCases(TestAccumulatorBase):
14
15 def case_0_regression(self):
16 for i in range(40):
17 lst = ["divwo 3, 1, 2"]
18 initial_regs = [0] * 32
19 initial_regs[1] = 0xbc716835f32ac00c
20 initial_regs[2] = 0xcdf69a7f7042db66
21 with Program(lst, bigendian) as prog:
22 self.add_case(prog, initial_regs)
23
24 def case_1_regression(self):
25 lst = ["divwo 3, 1, 2"]
26 initial_regs = [0] * 32
27 initial_regs[1] = 0x10000000000000000-4
28 initial_regs[2] = 0x10000000000000000-2
29 with Program(lst, bigendian) as prog:
30 self.add_case(prog, initial_regs)
31
32 def case_2_regression(self):
33 lst = ["divwo 3, 1, 2"]
34 initial_regs = [0] * 32
35 initial_regs[1] = 0xffffffffffff9321
36 initial_regs[2] = 0xffffffffffff7012
37 with Program(lst, bigendian) as prog:
38 self.add_case(prog, initial_regs)
39
40 def case_3_regression(self):
41 lst = ["divwo. 3, 1, 2"]
42 initial_regs = [0] * 32
43 initial_regs[1] = 0x1b8e32f2458746af
44 initial_regs[2] = 0x6b8aee2ccf7d62e9
45 with Program(lst, bigendian) as prog:
46 self.add_case(prog, initial_regs)
47
48 def case_4_regression(self):
49 lst = ["divw 3, 1, 2"]
50 initial_regs = [0] * 32
51 initial_regs[1] = 0x1c4e6c2f3aa4a05c
52 initial_regs[2] = 0xe730c2eed6cc8dd7
53 with Program(lst, bigendian) as prog:
54 self.add_case(prog, initial_regs)
55
56 def case_5_regression(self):
57 lst = ["divw 3, 1, 2",
58 "divwo. 6, 4, 5"]
59 initial_regs = [0] * 32
60 initial_regs[1] = 0x1c4e6c2f3aa4a05c
61 initial_regs[2] = 0xe730c2eed6cc8dd7
62 initial_regs[4] = 0x1b8e32f2458746af
63 initial_regs[5] = 0x6b8aee2ccf7d62e9
64 with Program(lst, bigendian) as prog:
65 self.add_case(prog, initial_regs)
66
67 def case_6_regression(self):
68 # CR0 not getting set properly for this one
69 # turns out that overflow is not set correctly in
70 # fu/div/output_stage.py calc_overflow
71 # https://bugs.libre-soc.org/show_bug.cgi?id=425
72 lst = ["divw. 3, 1, 2"]
73 initial_regs = [0] * 32
74 initial_regs[1] = 0x61c1cc3b80f2a6af
75 initial_regs[2] = 0x9dc66a7622c32bc0
76 with Program(lst, bigendian) as prog:
77 self.add_case(prog, initial_regs)
78
79 def case_7_regression(self):
80 # https://bugs.libre-soc.org/show_bug.cgi?id=425
81 lst = ["divw. 3, 1, 2"]
82 initial_regs = [0] * 32
83 initial_regs[1] = 0xf1791627e05e8096
84 initial_regs[2] = 0xffc868bf4573da0b
85 with Program(lst, bigendian) as prog:
86 self.add_case(prog, initial_regs)
87
88 def case_8_fsm_regression(self): # FSM result is "36" not 6
89 lst = ["divwu. 3, 1, 2"]
90 initial_regs = [0] * 32
91 initial_regs[1] = 18
92 initial_regs[2] = 3
93 with Program(lst, bigendian) as prog:
94 self.add_case(prog, initial_regs)
95
96 def case_9_regression(self): # CR0 fails: expected 0b10, actual 0b11
97 lst = ["divw. 3, 1, 2"]
98 initial_regs = [0] * 32
99 initial_regs[1] = 1
100 initial_regs[2] = 0
101 with Program(lst, bigendian) as prog:
102 self.add_case(prog, initial_regs)
103
104 @skip_case("causes test_issuer to go permanently busy!")
105 def case_10_regression(self): # overflow fails
106 lst = ["divwo 3, 1, 2"]
107 initial_regs = [0] * 32
108 initial_regs[1] = 0xbc716835f32ac00c
109 initial_regs[2] = 0xcdf69a7f7042db66
110 with Program(lst, bigendian) as prog:
111 self.add_case(prog, initial_regs)
112
113 def case_divw_by_zero_1(self):
114 lst = ["divw. 3, 1, 2"]
115 initial_regs = [0] * 32
116 initial_regs[1] = 0x1
117 initial_regs[2] = 0x0
118 with Program(lst, bigendian) as prog:
119 self.add_case(prog, initial_regs)
120
121 def case_divw_overflow2(self):
122 lst = ["divw. 3, 1, 2"]
123 initial_regs = [0] * 32
124 initial_regs[1] = 0x80000000
125 initial_regs[2] = 0xffffffffffffffff # top bits don't seem to matter
126 with Program(lst, bigendian) as prog:
127 self.add_case(prog, initial_regs)
128
129 def case_divw_overflow3(self):
130 lst = ["divw. 3, 1, 2"]
131 initial_regs = [0] * 32
132 initial_regs[1] = 0x80000000
133 initial_regs[2] = 0xffffffff
134 with Program(lst, bigendian) as prog:
135 self.add_case(prog, initial_regs)
136
137 def case_divwuo_regression_1(self):
138 lst = ["divwuo. 3, 1, 2"]
139 initial_regs = [0] * 32
140 initial_regs[1] = 0x7591a398c4e32b68
141 initial_regs[2] = 0x48674ab432867d69
142 with Program(lst, bigendian) as prog:
143 self.add_case(prog, initial_regs)
144
145 def case_divwuo_1(self):
146 lst = ["divwuo. 3, 1, 2"]
147 initial_regs = [0] * 32
148 initial_regs[1] = 0x50
149 initial_regs[2] = 0x2
150 with Program(lst, bigendian) as prog:
151 self.add_case(prog, initial_regs)
152
153 def case_rand_divwu(self):
154 insns = ["divwu", "divwu.", "divwuo", "divwuo."]
155 for i in range(40):
156 choice = random.choice(insns)
157 lst = [f"{choice} 3, 1, 2"]
158 initial_regs = [0] * 32
159 initial_regs[1] = log_rand(32)
160 initial_regs[2] = log_rand(32)
161 with Program(lst, bigendian) as prog:
162 self.add_case(prog, initial_regs)
163
164 def case_rand_divw(self):
165 insns = ["divw", "divw.", "divwo", "divwo."]
166 for i in range(40):
167 choice = random.choice(insns)
168 lst = [f"{choice} 3, 1, 2"]
169 initial_regs = [0] * 32
170 initial_regs[1] = log_rand(32)
171 initial_regs[2] = log_rand(32)
172 with Program(lst, bigendian) as prog:
173 self.add_case(prog, initial_regs)
174
175
176 class TestPipe(DivTestHelper):
177 def test_div_pipe_core(self):
178 self.run_all(DivTestCases().test_data,
179 DivPipeKind.DivPipeCore, "div_pipe_caller")
180
181 def test_fsm_div_core(self):
182 self.run_all(DivTestCases().test_data,
183 DivPipeKind.FSMDivCore, "div_pipe_caller")
184
185 def test_sim_only(self):
186 self.run_all(DivTestCases().test_data,
187 DivPipeKind.SimOnly, "div_pipe_caller")
188
189
190 if __name__ == "__main__":
191 unittest.main()