src/soc/fu/div/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.div.pipeline import DIVBasePipe
  17 from soc.fu.div.pipe_data import DIVPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to DIVFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
  29     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
  30
  31     print ("alu get_cu_inputs", res)
  32
  33     return res
  34
  35
  36
  37 def set_alu_inputs(alu, dec2, sim):
  38     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  39     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  40     # and place it into data_i.b
  41
  42     inp = yield from get_cu_inputs(dec2, sim)
  43     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  44     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  45
  46     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  47     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  48
  49
  50 # This test bench is a bit different than is usual. Initially when I
  51 # was writing it, I had all of the tests call a function to create a
  52 # device under test and simulator, initialize the dut, run the
  53 # simulation for ~2 cycles, and assert that the dut output what it
  54 # should have. However, this was really slow, since it needed to
  55 # create and tear down the dut and simulator for every test case.
  56
  57 # Now, instead of doing that, every test case in DIVTestCase puts some
  58 # data into the test_data list below, describing the instructions to
  59 # be tested and the initial state. Once all the tests have been run,
  60 # test_data gets passed to TestRunner which then sets up the DUT and
  61 # simulator once, runs all the data through it, and asserts that the
  62 # results match the pseudocode sim at every cycle.
  63
  64 # By doing this, I've reduced the time it takes to run the test suite
  65 # massively. Before, it took around 1 minute on my computer, now it
  66 # takes around 3 seconds
  67
  68
  69 class DIVTestCase(FHDLTestCase):
  70     test_data = []
  71
  72     def __init__(self, name):
  73         super().__init__(name)
  74         self.test_name = name
  75
  76     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  77         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  78         self.test_data.append(tc)
  79
  80     def test_rand_divw(self):
  81         insns = ["divw", "divw.", "divwo", "divwo."]
  82         for i in range(40):
  83             choice = random.choice(insns)
  84             lst = [f"{choice} 3, 1, 2"]
  85             initial_regs = [0] * 32
  86             initial_regs[1] = random.randint(0, (1<<64)-1)
  87             initial_regs[2] = random.randint(0, (1<<64)-1)
  88             self.run_tst_program(Program(lst), initial_regs)
  89
  90     def test_ilang(self):
  91         pspec = DIVPipeSpec(id_wid=2)
  92         alu = DIVBasePipe(pspec)
  93         vl = rtlil.convert(alu, ports=alu.ports())
  94         with open("alu_pipeline.il", "w") as f:
  95             f.write(vl)
  96
  97
  98 class TestRunner(FHDLTestCase):
  99     def __init__(self, test_data):
 100         super().__init__("run_all")
 101         self.test_data = test_data
 102
 103     def run_all(self):
 104         m = Module()
 105         comb = m.d.comb
 106         instruction = Signal(32)
 107
 108         pdecode = create_pdecode()
 109
 110         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 111
 112         pspec = DIVPipeSpec(id_wid=2)
 113         m.submodules.alu = alu = DIVBasePipe(pspec)
 114
 115         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 116         comb += alu.p.valid_i.eq(1)
 117         comb += alu.n.ready_i.eq(1)
 118         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 119         sim = Simulator(m)
 120
 121         sim.add_clock(1e-6)
 122         def process():
 123             for test in self.test_data:
 124                 print(test.name)
 125                 program = test.program
 126                 self.subTest(test.name)
 127                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 128                                 test.mem, test.msr)
 129                 gen = program.generate_instructions()
 130                 instructions = list(zip(gen, program.assembly.splitlines()))
 131
 132                 index = sim.pc.CIA.value//4
 133                 while index < len(instructions):
 134                     ins, code = instructions[index]
 135
 136                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 137                     print(code)
 138                     if 'XER' in sim.spr:
 139                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 140                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 141                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 142                         print ("before: so/ov/32", so, ov, ov32)
 143
 144                     # ask the decoder to decode this binary data (endian'd)
 145                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 146                     yield instruction.eq(ins)          # raw binary instr.
 147                     yield Settle()
 148                     fn_unit = yield pdecode2.e.do.fn_unit
 149                     self.assertEqual(fn_unit, Function.DIV.value)
 150                     yield from set_alu_inputs(alu, pdecode2, sim)
 151                     yield
 152                     opname = code.split(' ')[0]
 153                     yield from sim.call(opname)
 154                     index = sim.pc.CIA.value//4
 155
 156                     vld = yield alu.n.valid_o
 157                     while not vld:
 158                         yield
 159                         vld = yield alu.n.valid_o
 160                     yield
 161
 162                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 163
 164         sim.add_sync_process(process)
 165         with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
 166                             traces=[]):
 167             sim.run()
 168
 169     def check_alu_outputs(self, alu, dec2, sim, code):
 170
 171         rc = yield dec2.e.do.rc.data
 172         cridx_ok = yield dec2.e.write_cr.ok
 173         cridx = yield dec2.e.write_cr.data
 174
 175         print ("check extra output", repr(code), cridx_ok, cridx)
 176         if rc:
 177             self.assertEqual(cridx, 0, code)
 178
 179         oe = yield dec2.e.do.oe.oe
 180         oe_ok = yield dec2.e.do.oe.ok
 181         if not oe or not oe_ok:
 182             # if OE not enabled, XER SO and OV must correspondingly be false
 183             so_ok = yield alu.n.data_o.xer_so.ok
 184             ov_ok = yield alu.n.data_o.xer_ov.ok
 185             self.assertEqual(so_ok, False, code)
 186             self.assertEqual(ov_ok, False, code)
 187
 188         sim_o = {}
 189         res = {}
 190
 191         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 192         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 193         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 194         yield from ALUHelpers.get_int_o(res, alu, dec2)
 195         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 196
 197         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 198         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 199         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 200         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 201         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 202
 203         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 204         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 205         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 206         ALUHelpers.check_int_o(self, res, sim_o, code)
 207         ALUHelpers.check_xer_so(self, res, sim_o, code)
 208
 209
 210 if __name__ == "__main__":
 211     unittest.main(exit=False)
 212     suite = unittest.TestSuite()
 213     suite.addTest(TestRunner(DIVTestCase.test_data))
 214
 215     runner = unittest.TextTestRunner()
 216     runner.run(suite)