src/soc/fu/div/test/test_pipe_caller.py

   1 import random
   2 import unittest
   3 from nmigen import Module, Signal
   4 from nmigen.back.pysim import Simulator, Delay
   5 from nmigen.cli import rtlil
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.decoder.power_enums import XER_bits, Function
   9 from soc.simulator.program import Program
  10 from soc.decoder.isa.all import ISA
  11 from soc.config.endian import bigendian
  12
  13 from soc.fu.test.common import (TestCase, ALUHelpers)
  14 from soc.fu.div.pipeline import DivBasePipe
  15 from soc.fu.div.pipe_data import DivPipeSpec, DivPipeKind
  16
  17
  18 def log_rand(n, min_val=1):
  19     logrange = random.randint(1, n)
  20     return random.randint(min_val, (1 << logrange)-1)
  21
  22
  23 def get_cu_inputs(dec2, sim):
  24     """naming (res) must conform to DivFunctionUnit input regspec
  25     """
  26     res = {}
  27
  28     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  29     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  30     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  31
  32     print("alu get_cu_inputs", res)
  33
  34     return res
  35
  36
  37 def set_alu_inputs(alu, dec2, sim):
  38     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  39     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  40     # and place it into data_i.b
  41
  42     inp = yield from get_cu_inputs(dec2, sim)
  43     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  44     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  45
  46     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  47
  48
  49 # This test bench is a bit different than is usual. Initially when I
  50 # was writing it, I had all of the tests call a function to create a
  51 # device under test and simulator, initialize the dut, run the
  52 # simulation for ~2 cycles, and assert that the dut output what it
  53 # should have. However, this was really slow, since it needed to
  54 # create and tear down the dut and simulator for every test case.
  55
  56 # Now, instead of doing that, every test case in DivTestCase puts some
  57 # data into the test_data list below, describing the instructions to
  58 # be tested and the initial state. Once all the tests have been run,
  59 # test_data gets passed to TestRunner which then sets up the DUT and
  60 # simulator once, runs all the data through it, and asserts that the
  61 # results match the pseudocode sim at every cycle.
  62
  63 # By doing this, I've reduced the time it takes to run the test suite
  64 # massively. Before, it took around 1 minute on my computer, now it
  65 # takes around 3 seconds
  66
  67
  68 class DivTestCases:
  69     def __init__(self):
  70         self.test_data = []
  71         for n, v in self.__class__.__dict__.items():
  72             if n.startswith("test") and callable(v):
  73                 self._current_test_name = n
  74                 v(self)
  75
  76     def run_test_program(self, prog, initial_regs=None, initial_sprs=None):
  77         tc = TestCase(prog, self._current_test_name,
  78                       initial_regs, initial_sprs)
  79         self.test_data.append(tc)
  80
  81     def tst_0_regression(self):
  82         for i in range(40):
  83             lst = ["divwo 3, 1, 2"]
  84             initial_regs = [0] * 32
  85             initial_regs[1] = 0xbc716835f32ac00c
  86             initial_regs[2] = 0xcdf69a7f7042db66
  87             self.run_test_program(Program(lst, bigendian), initial_regs)
  88
  89     def tst_1_regression(self):
  90         lst = ["divwo 3, 1, 2"]
  91         initial_regs = [0] * 32
  92         initial_regs[1] = 0x10000000000000000-4
  93         initial_regs[2] = 0x10000000000000000-2
  94         self.run_test_program(Program(lst, bigendian), initial_regs)
  95
  96     def tst_2_regression(self):
  97         lst = ["divwo 3, 1, 2"]
  98         initial_regs = [0] * 32
  99         initial_regs[1] = 0xffffffffffff9321
 100         initial_regs[2] = 0xffffffffffff7012
 101         self.run_test_program(Program(lst, bigendian), initial_regs)
 102
 103     def tst_3_regression(self):
 104         lst = ["divwo. 3, 1, 2"]
 105         initial_regs = [0] * 32
 106         initial_regs[1] = 0x1b8e32f2458746af
 107         initial_regs[2] = 0x6b8aee2ccf7d62e9
 108         self.run_test_program(Program(lst, bigendian), initial_regs)
 109
 110     def tst_4_regression(self):
 111         lst = ["divw 3, 1, 2"]
 112         initial_regs = [0] * 32
 113         initial_regs[1] = 0x1c4e6c2f3aa4a05c
 114         initial_regs[2] = 0xe730c2eed6cc8dd7
 115         self.run_test_program(Program(lst, bigendian), initial_regs)
 116
 117     def tst_5_regression(self):
 118         lst = ["divw 3, 1, 2",
 119                "divwo. 6, 4, 5"]
 120         initial_regs = [0] * 32
 121         initial_regs[1] = 0x1c4e6c2f3aa4a05c
 122         initial_regs[2] = 0xe730c2eed6cc8dd7
 123         initial_regs[4] = 0x1b8e32f2458746af
 124         initial_regs[5] = 0x6b8aee2ccf7d62e9
 125         self.run_test_program(Program(lst, bigendian), initial_regs)
 126
 127     def tst_6_regression(self):
 128         # CR0 not getting set properly for this one
 129         # turns out that overflow is not set correctly in
 130         # fu/div/output_stage.py calc_overflow
 131         # https://bugs.libre-soc.org/show_bug.cgi?id=425
 132         lst = ["divw. 3, 1, 2"]
 133         initial_regs = [0] * 32
 134         initial_regs[1] = 0x61c1cc3b80f2a6af
 135         initial_regs[2] = 0x9dc66a7622c32bc0
 136         self.run_test_program(Program(lst, bigendian), initial_regs)
 137
 138     def tst_7_regression(self):
 139         # https://bugs.libre-soc.org/show_bug.cgi?id=425
 140         lst = ["divw. 3, 1, 2"]
 141         initial_regs = [0] * 32
 142         initial_regs[1] = 0xf1791627e05e8096
 143         initial_regs[2] = 0xffc868bf4573da0b
 144         self.run_test_program(Program(lst, bigendian), initial_regs)
 145
 146     def tst_divw_by_zero_1(self):
 147         lst = ["divw. 3, 1, 2"]
 148         initial_regs = [0] * 32
 149         initial_regs[1] = 0x1
 150         initial_regs[2] = 0x0
 151         self.run_test_program(Program(lst, bigendian), initial_regs)
 152
 153     def tst_divw_overflow2(self):
 154         lst = ["divw. 3, 1, 2"]
 155         initial_regs = [0] * 32
 156         initial_regs[1] = 0x80000000
 157         initial_regs[2] = 0xffffffffffffffff  # top bits don't seem to matter
 158         self.run_test_program(Program(lst, bigendian), initial_regs)
 159
 160     def tst_divw_overflow3(self):
 161         lst = ["divw. 3, 1, 2"]
 162         initial_regs = [0] * 32
 163         initial_regs[1] = 0x80000000
 164         initial_regs[2] = 0xffffffff
 165         self.run_test_program(Program(lst, bigendian), initial_regs)
 166
 167     def tst_divwuo_regression_1(self):
 168         lst = ["divwuo. 3, 1, 2"]
 169         initial_regs = [0] * 32
 170         initial_regs[1] = 0x7591a398c4e32b68
 171         initial_regs[2] = 0x48674ab432867d69
 172         self.run_test_program(Program(lst, bigendian), initial_regs)
 173
 174     def tst_divwuo_1(self):
 175         lst = ["divwuo. 3, 1, 2"]
 176         initial_regs = [0] * 32
 177         initial_regs[1] = 0x50
 178         initial_regs[2] = 0x2
 179         self.run_test_program(Program(lst, bigendian), initial_regs)
 180
 181     def test_all(self):
 182         instrs = []
 183         for width in ("w", "d"):
 184             for sign in ("", "u"):
 185                 for ov in ("", "o"):
 186                     for cnd in ("", "."):
 187                         instrs += ["div" + width + sign + ov + cnd,
 188                                    "div" + width + "e" + sign + ov + cnd]
 189             for sign in ("s", "u"):
 190                 instrs += ["mod" + sign + width]
 191         test_values = [
 192             0x0,
 193             0x1,
 194             0x2,
 195             0xFFFF_FFFF_FFFF_FFFF,
 196             0xFFFF_FFFF_FFFF_FFFE,
 197             0x7FFF_FFFF_FFFF_FFFF,
 198             0x8000_0000_0000_0000,
 199             0x1234_5678_0000_0000,
 200             0x1234_5678_8000_0000,
 201             0x1234_5678_FFFF_FFFF,
 202             0x1234_5678_7FFF_FFFF,
 203         ]
 204         for instr in instrs:
 205             l = [f"{instr} 3, 1, 2"]
 206             for ra in test_values:
 207                 for rb in test_values:
 208                     initial_regs = [0] * 32
 209                     initial_regs[1] = ra
 210                     initial_regs[2] = rb
 211                     prog = Program(l, bigendian)
 212                     self.run_test_program(prog, initial_regs)
 213
 214     def tst_rand_divwu(self):
 215         insns = ["divwu", "divwu.", "divwuo", "divwuo."]
 216         for i in range(40):
 217             choice = random.choice(insns)
 218             lst = [f"{choice} 3, 1, 2"]
 219             initial_regs = [0] * 32
 220             initial_regs[1] = log_rand(32)
 221             initial_regs[2] = log_rand(32)
 222             self.run_test_program(Program(lst, bigendian), initial_regs)
 223
 224     def tst_rand_divw(self):
 225         insns = ["divw", "divw.", "divwo", "divwo."]
 226         for i in range(40):
 227             choice = random.choice(insns)
 228             lst = [f"{choice} 3, 1, 2"]
 229             initial_regs = [0] * 32
 230             initial_regs[1] = log_rand(32)
 231             initial_regs[2] = log_rand(32)
 232             self.run_test_program(Program(lst, bigendian), initial_regs)
 233
 234
 235 class TestRunner(unittest.TestCase):
 236     def write_ilang(self, div_pipe_kind):
 237         pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
 238         alu = DivBasePipe(pspec)
 239         vl = rtlil.convert(alu, ports=alu.ports())
 240         with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
 241             f.write(vl)
 242
 243     def test_write_ilang_div_pipe_core(self):
 244         self.write_ilang(DivPipeKind.DivPipeCore)
 245
 246     def test_write_ilang_fsm_div_core(self):
 247         self.write_ilang(DivPipeKind.FSMDivCore)
 248
 249     def test_write_ilang_sim_only(self):
 250         self.write_ilang(DivPipeKind.SimOnly)
 251
 252     def run_all(self, div_pipe_kind):
 253         test_data = DivTestCases().test_data
 254         m = Module()
 255         comb = m.d.comb
 256         instruction = Signal(32)
 257
 258         pdecode = create_pdecode()
 259
 260         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 261
 262         pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
 263         m.submodules.alu = alu = DivBasePipe(pspec)
 264
 265         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 266         comb += alu.n.ready_i.eq(1)
 267         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 268         sim = Simulator(m)
 269
 270         sim.add_clock(1e-6)
 271
 272         def process():
 273             for test in test_data:
 274                 print(test.name)
 275                 program = test.program
 276                 with self.subTest(test.name):
 277                     isa_sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 278                                   test.mem, test.msr,
 279                                   bigendian=bigendian)
 280                     gen = program.generate_instructions()
 281                     instructions = list(
 282                         zip(gen, program.assembly.splitlines()))
 283                     yield Delay(0.1e-6)
 284
 285                     index = isa_sim.pc.CIA.value//4
 286                     while index < len(instructions):
 287                         ins, code = instructions[index]
 288
 289                         print("instruction: 0x{:X}".format(ins & 0xffffffff))
 290                         print(code)
 291                         if 'XER' in isa_sim.spr:
 292                             so = 1 if isa_sim.spr['XER'][XER_bits['SO']] else 0
 293                             ov = 1 if isa_sim.spr['XER'][XER_bits['OV']] else 0
 294                             ov32 = 1 if isa_sim.spr['XER'][XER_bits['OV32']] else 0
 295                             print("before: so/ov/32", so, ov, ov32)
 296
 297                         # ask the decoder to decode this binary data (endian'd)
 298                         # little / big?
 299                         yield pdecode2.dec.bigendian.eq(bigendian)
 300                         yield instruction.eq(ins)          # raw binary instr.
 301                         yield Delay(0.1e-6)
 302                         fn_unit = yield pdecode2.e.do.fn_unit
 303                         self.assertEqual(fn_unit, Function.DIV.value)
 304                         yield from set_alu_inputs(alu, pdecode2, isa_sim)
 305
 306                         # set valid for one cycle, propagate through pipeline...
 307                         yield alu.p.valid_i.eq(1)
 308                         yield
 309                         yield alu.p.valid_i.eq(0)
 310
 311                         opname = code.split(' ')[0]
 312                         yield from isa_sim.call(opname)
 313                         index = isa_sim.pc.CIA.value//4
 314
 315                         vld = yield alu.n.valid_o
 316                         while not vld:
 317                             yield
 318                             yield Delay(0.1e-6)
 319                             vld = yield alu.n.valid_o
 320                             # bug #425 investigation
 321                             do = alu.pipe_end.div_out
 322                             ctx_op = do.i.ctx.op
 323                             is_32bit = yield ctx_op.is_32bit
 324                             is_signed = yield ctx_op.is_signed
 325                             quotient_root = yield do.i.core.quotient_root
 326                             quotient_65 = yield do.quotient_65
 327                             dive_abs_ov32 = yield do.i.dive_abs_ov32
 328                             div_by_zero = yield do.i.div_by_zero
 329                             quotient_neg = yield do.quotient_neg
 330                             print("32bit", hex(is_32bit))
 331                             print("signed", hex(is_signed))
 332                             print("quotient_root", hex(quotient_root))
 333                             print("quotient_65", hex(quotient_65))
 334                             print("div_by_zero", hex(div_by_zero))
 335                             print("dive_abs_ov32", hex(dive_abs_ov32))
 336                             print("quotient_neg", hex(quotient_neg))
 337                             print("")
 338                         yield
 339
 340                         yield Delay(0.1e-6)
 341                         print("time:", sim._state.timeline.now)
 342                         yield from self.check_alu_outputs(alu, pdecode2, isa_sim, code)
 343
 344         sim.add_sync_process(process)
 345         with sim.write_vcd(f"div_simulator_{div_pipe_kind.name}.vcd",
 346                            f"div_simulator_{div_pipe_kind.name}.gtkw",
 347                            traces=[]):
 348             sim.run()
 349
 350     def check_alu_outputs(self, alu, dec2, sim, code):
 351
 352         rc = yield dec2.e.do.rc.data
 353         cridx_ok = yield dec2.e.write_cr.ok
 354         cridx = yield dec2.e.write_cr.data
 355
 356         print("check extra output", repr(code), cridx_ok, cridx)
 357         if rc:
 358             self.assertEqual(cridx, 0, code)
 359
 360         sim_o = {}
 361         res = {}
 362
 363         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 364         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 365         yield from ALUHelpers.get_int_o(res, alu, dec2)
 366         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 367
 368         print("res output", res)
 369
 370         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 371         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 372         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 373         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 374
 375         print("sim output", sim_o)
 376
 377         ALUHelpers.check_int_o(self, res, sim_o, code)
 378         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 379         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 380         ALUHelpers.check_xer_so(self, res, sim_o, code)
 381
 382         oe = yield dec2.e.do.oe.oe
 383         oe_ok = yield dec2.e.do.oe.ok
 384         print("oe, oe_ok", oe, oe_ok)
 385         if not oe or not oe_ok:
 386             # if OE not enabled, XER SO and OV must not be activated
 387             so_ok = yield alu.n.data_o.xer_so.ok
 388             ov_ok = yield alu.n.data_o.xer_ov.ok
 389             print("so, ov", so_ok, ov_ok)
 390             self.assertEqual(ov_ok, False, code)
 391             self.assertEqual(so_ok, False, code)
 392
 393     def test_run_div_pipe_core(self):
 394         self.run_all(DivPipeKind.DivPipeCore)
 395
 396     def test_run_fsm_div_core(self):
 397         self.run_all(DivPipeKind.FSMDivCore)
 398
 399     def test_run_sim_only(self):
 400         self.run_all(DivPipeKind.SimOnly)
 401
 402
 403 if __name__ == "__main__":
 404     unittest.main()