Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / div / test / test_pipe_ilang.py
1 import unittest
2 from nmigen.cli import rtlil
3 from soc.fu.div.pipe_data import DivPipeSpec, DivPipeKind
4 from soc.fu.div.pipeline import DivBasePipe
5
6
7 class TestPipeIlang(unittest.TestCase):
8 def write_ilang(self, div_pipe_kind):
9 pspec = DivPipeSpec(
10 id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=None)
11 alu = DivBasePipe(pspec)
12 vl = rtlil.convert(alu, ports=alu.ports())
13 with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
14 f.write(vl)
15
16 def test_div_pipe_core(self):
17 self.write_ilang(DivPipeKind.DivPipeCore)
18
19 def test_fsm_div_core(self):
20 self.write_ilang(DivPipeKind.FSMDivCore)
21
22 def test_sim_only(self):
23 self.write_ilang(DivPipeKind.SimOnly)
24
25
26 if __name__ == "__main__":
27 unittest.main()