2 from nmigen
.cli
import rtlil
3 from soc
.fu
.div
.pipe_data
import DivPipeSpec
, DivPipeKind
4 from soc
.fu
.div
.pipeline
import DivBasePipe
7 class TestPipeIlang(unittest
.TestCase
):
8 def write_ilang(self
, div_pipe_kind
):
10 id_wid
=2, div_pipe_kind
=div_pipe_kind
, parent_pspec
=None)
11 alu
= DivBasePipe(pspec
)
12 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
13 with
open(f
"div_pipeline_{div_pipe_kind.name}.il", "w") as f
:
16 def test_div_pipe_core(self
):
17 self
.write_ilang(DivPipeKind
.DivPipeCore
)
19 def test_fsm_div_core(self
):
20 self
.write_ilang(DivPipeKind
.FSMDivCore
)
22 def test_sim_only(self
):
23 self
.write_ilang(DivPipeKind
.SimOnly
)
26 if __name__
== "__main__":