src/soc/fu/ldst/loadstore.py

   1 """LoadStore1 FSM.
   2
   3 based on microwatt loadstore1.vhdl, but conforming to PortInterface.
   4 unlike loadstore1.vhdl this does *not* deal with actual Load/Store
   5 ops: that job is handled by LDSTCompUnit, which talks to LoadStore1
   6 by way of PortInterface.  PortInterface is where things need extending,
   7 such as adding dcbz support, etc.
   8
   9 this module basically handles "pure" load / store operations, and
  10 its first job is to ask the D-Cache for the data.  if that fails,
  11 the second task (if virtual memory is enabled) is to ask the MMU
  12 to perform a TLB, then to go *back* to the cache and ask again.
  13
  14 Links:
  15
  16 * https://bugs.libre-soc.org/show_bug.cgi?id=465
  17
  18 """
  19
  20 from nmigen import (Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux,
  21                     Record, Memory,
  22                     Const)
  23 from nmutil.util import rising_edge
  24 from enum import Enum, unique
  25
  26 from soc.experiment.dcache import DCache
  27 from soc.experiment.pimem import PortInterfaceBase
  28 from soc.experiment.mem_types import LoadStore1ToMMUType
  29 from soc.experiment.mem_types import MMUToLoadStore1Type
  30
  31 from soc.minerva.wishbone import make_wb_layout
  32 from soc.bus.sram import SRAM
  33
  34
  35 @unique
  36 class State(Enum):
  37     IDLE = 0       # ready for instruction
  38     ACK_WAIT = 1   # waiting for ack from dcache
  39     MMU_LOOKUP = 2 # waiting for MMU to look up translation
  40     TLBIE_WAIT = 3 # waiting for MMU to finish doing a tlbie
  41
  42
  43 # glue logic for microwatt mmu and dcache
  44 class LoadStore1(PortInterfaceBase):
  45     def __init__(self, pspec):
  46         self.pspec = pspec
  47         self.disable_cache = (hasattr(pspec, "disable_cache") and
  48                               pspec.disable_cache == True)
  49         regwid = pspec.reg_wid
  50         addrwid = pspec.addr_wid
  51
  52         super().__init__(regwid, addrwid)
  53         self.dcache = DCache()
  54         # these names are from the perspective of here (LoadStore1)
  55         self.d_out  = self.dcache.d_in     # in to dcache is out for LoadStore
  56         self.d_in = self.dcache.d_out      # out from dcache is in for LoadStore
  57         self.m_out  = LoadStore1ToMMUType() # out *to* MMU
  58         self.m_in = MMUToLoadStore1Type()   # in *from* MMU
  59
  60         # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
  61         self.dbus = Record(make_wb_layout(pspec))
  62
  63         # for creating a single clock blip to DCache
  64         self.d_valid = Signal()
  65         self.d_w_valid = Signal()
  66         self.d_validblip = Signal()
  67
  68         # DSISR and DAR cached values.  note that the MMU FSM is where
  69         # these are accessed by OP_MTSPR/OP_MFSPR, on behalf of LoadStore1.
  70         # by contrast microwatt has the spr set/get done *in* loadstore1.vhdl
  71         self.dsisr = Signal(64)
  72         self.dar = Signal(64)
  73
  74         # state info for LD/ST
  75         self.done          = Signal()
  76         # latch most of the input request
  77         self.load          = Signal()
  78         self.tlbie         = Signal()
  79         self.dcbz          = Signal()
  80         self.addr          = Signal(64)
  81         self.store_data    = Signal(64)
  82         self.load_data     = Signal(64)
  83         self.byte_sel      = Signal(8)
  84         self.update        = Signal()
  85         #self.xerc         : xer_common_t;
  86         #self.reserve       = Signal()
  87         #self.atomic        = Signal()
  88         #self.atomic_last   = Signal()
  89         #self.rc            = Signal()
  90         self.nc            = Signal()              # non-cacheable access
  91         self.virt_mode     = Signal()
  92         self.priv_mode     = Signal()
  93         self.state        = Signal(State)
  94         self.instr_fault   = Signal()
  95         self.align_intr    = Signal()
  96         self.busy          = Signal()
  97         self.wait_dcache   = Signal()
  98         self.wait_mmu      = Signal()
  99         #self.mode_32bit    = Signal()
 100         self.wr_sel        = Signal(2)
 101         self.interrupt     = Signal()
 102         #self.intr_vec     : integer range 0 to 16#fff#;
 103         #self.nia           = Signal(64)
 104         #self.srr1          = Signal(16)
 105
 106     def set_wr_addr(self, m, addr, mask, misalign):
 107         m.d.comb += self.load.eq(0) # store operation
 108
 109         m.d.comb += self.d_out.load.eq(0)
 110         m.d.comb += self.byte_sel.eq(mask)
 111         m.d.comb += self.addr.eq(addr)
 112         m.d.comb += self.align_intr.eq(misalign)
 113         # option to disable the cache entirely for write
 114         if self.disable_cache:
 115             m.d.comb += self.nc.eq(1)
 116         return None
 117
 118     def set_rd_addr(self, m, addr, mask, misalign):
 119         m.d.comb += self.d_valid.eq(1)
 120         m.d.comb += self.d_out.valid.eq(self.d_validblip)
 121         m.d.comb += self.load.eq(1) # load operation
 122         m.d.comb += self.d_out.load.eq(1)
 123         m.d.comb += self.byte_sel.eq(mask)
 124         m.d.comb += self.align_intr.eq(misalign)
 125         m.d.comb += self.addr.eq(addr)
 126         # BAD HACK! disable cacheing on LD when address is 0xCxxx_xxxx
 127         # this is for peripherals. same thing done in Microwatt loadstore1.vhdl
 128         with m.If(addr[28:] == Const(0xc, 4)):
 129             m.d.comb += self.nc.eq(1)
 130         # option to disable the cache entirely for read
 131         if self.disable_cache:
 132             m.d.comb += self.nc.eq(1)
 133         return None #FIXME return value
 134
 135     def set_wr_data(self, m, data, wen):
 136         # do the "blip" on write data
 137         m.d.comb += self.d_valid.eq(1)
 138         m.d.comb += self.d_out.valid.eq(self.d_validblip)
 139         # put data into comb which is picked up in main elaborate()
 140         m.d.comb += self.d_w_valid.eq(1)
 141         m.d.comb += self.store_data.eq(data)
 142         #m.d.sync += self.d_out.byte_sel.eq(wen) # this might not be needed
 143         st_ok = self.done # TODO indicates write data is valid
 144         return st_ok
 145
 146     def get_rd_data(self, m):
 147         ld_ok = self.done     # indicates read data is valid
 148         data = self.load_data # actual read data
 149         return data, ld_ok
 150
 151     def elaborate(self, platform):
 152         m = super().elaborate(platform)
 153         comb, sync = m.d.comb, m.d.sync
 154
 155         # create dcache module
 156         m.submodules.dcache = dcache = self.dcache
 157
 158         # temp vars
 159         d_out, d_in, m_in, dbus = self.d_out, self.d_in, self.m_in, self.dbus
 160         exc = self.pi.exc_o
 161         exception = exc.happened
 162         mmureq = Signal()
 163
 164         # copy of address, but gets over-ridden for OP_FETCH_FAILED
 165         maddr = Signal(64)
 166         m.d.comb += maddr.eq(self.addr)
 167
 168         # create a blip (single pulse) on valid read/write request
 169         # this can be over-ridden in the FSM to get dcache to re-run
 170         # a request when MMU_LOOKUP completes
 171         m.d.comb += self.d_validblip.eq(rising_edge(m, self.d_valid))
 172
 173         # fsm skeleton
 174         with m.Switch(self.state):
 175             with m.Case(State.IDLE):
 176                 with m.If(self.d_validblip):
 177                     sync += self.state.eq(State.ACK_WAIT)
 178
 179             # waiting for completion
 180             with m.Case(State.ACK_WAIT):
 181
 182                 with m.If(d_in.error):
 183                     # cache error is not necessarily "final", it could
 184                     # be that it was just a TLB miss
 185                     with m.If(d_in.cache_paradox):
 186                         comb += exception.eq(1)
 187                         sync += self.state.eq(State.IDLE)
 188                         sync += self.dsisr[63 - 38].eq(~self.load)
 189                         # XXX there is no architected bit for this
 190                         # (probably should be a machine check in fact)
 191                         sync += self.dsisr[63 - 35].eq(d_in.cache_paradox)
 192
 193                     with m.Else():
 194                         # Look up the translation for TLB miss
 195                         # and also for permission error and RC error
 196                         # in case the PTE has been updated.
 197                         comb += mmureq.eq(1)
 198                         sync += self.state.eq(State.MMU_LOOKUP)
 199                 with m.If(d_in.valid):
 200                     m.d.comb += self.done.eq(1)
 201                     sync += self.state.eq(State.IDLE)
 202                     with m.If(self.load):
 203                         m.d.comb += self.load_data.eq(d_in.data)
 204
 205             # waiting here for the MMU TLB lookup to complete.
 206             # either re-try the dcache lookup or throw MMU exception
 207             with m.Case(State.MMU_LOOKUP):
 208                 with m.If(m_in.done):
 209                     with m.If(~self.instr_fault):
 210                         # retry the request now that the MMU has
 211                         # installed a TLB entry
 212                         m.d.comb += self.d_validblip.eq(1) # re-run dcache req
 213                         sync += self.state.eq(State.ACK_WAIT)
 214                     with m.Else():
 215                         # instruction lookup fault: store address in DAR
 216                         comb += exc.happened.eq(1)
 217                         sync += self.dar.eq(self.addr)
 218
 219                 with m.If(m_in.err):
 220                     # MMU RADIX exception thrown
 221                     comb += exception.eq(1)
 222                     sync += self.dsisr[63 - 33].eq(m_in.invalid)
 223                     sync += self.dsisr[63 - 36].eq(m_in.perm_error)
 224                     sync += self.dsisr[63 - 38].eq(self.load)
 225                     sync += self.dsisr[63 - 44].eq(m_in.badtree)
 226                     sync += self.dsisr[63 - 45].eq(m_in.rc_error)
 227
 228             with m.Case(State.TLBIE_WAIT):
 229                 pass
 230
 231         # alignment error: store address in DAR
 232         with m.If(self.align_intr):
 233             comb += exc.happened.eq(1)
 234             sync += self.dar.eq(self.addr)
 235
 236         # happened, alignment, instr_fault, invalid.
 237         # note that all of these flow through - eventually to the TRAP
 238         # pipeline, via PowerDecoder2.
 239         comb += exc.invalid.eq(m_in.invalid)
 240         comb += exc.alignment.eq(self.align_intr)
 241         comb += exc.instr_fault.eq(self.instr_fault)
 242         # badtree, perm_error, rc_error, segment_fault
 243         comb += exc.badtree.eq(m_in.badtree)
 244         comb += exc.perm_error.eq(m_in.perm_error)
 245         comb += exc.rc_error.eq(m_in.rc_error)
 246         comb += exc.segment_fault.eq(m_in.segerr)
 247
 248         # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
 249         comb += dbus.adr.eq(dcache.wb_out.adr)
 250         comb += dbus.dat_w.eq(dcache.wb_out.dat)
 251         comb += dbus.sel.eq(dcache.wb_out.sel)
 252         comb += dbus.cyc.eq(dcache.wb_out.cyc)
 253         comb += dbus.stb.eq(dcache.wb_out.stb)
 254         comb += dbus.we.eq(dcache.wb_out.we)
 255
 256         comb += dcache.wb_in.dat.eq(dbus.dat_r)
 257         comb += dcache.wb_in.ack.eq(dbus.ack)
 258         if hasattr(dbus, "stall"):
 259             comb += dcache.wb_in.stall.eq(dbus.stall)
 260
 261         # write out d data only when flag set
 262         with m.If(self.d_w_valid):
 263             m.d.sync += d_out.data.eq(self.store_data)
 264         with m.Else():
 265             m.d.sync += d_out.data.eq(0)
 266
 267         # this must move into the FSM, conditionally noticing that
 268         # the "blip" comes from self.d_validblip.
 269         # task 1: look up in dcache
 270         # task 2: if dcache fails, look up in MMU.
 271         # do **NOT** confuse the two.
 272         m.d.comb += d_out.load.eq(self.load)
 273         m.d.comb += d_out.byte_sel.eq(self.byte_sel)
 274         m.d.comb += d_out.addr.eq(self.addr)
 275         m.d.comb += d_out.nc.eq(self.nc)
 276
 277         # XXX these should be possible to remove but for some reason
 278         # cannot be... yet. TODO, investigate
 279         m.d.comb += self.done.eq(d_in.valid)
 280         m.d.comb += self.load_data.eq(d_in.data)
 281
 282         ''' TODO: translate to nmigen.
 283         -- Update outputs to MMU
 284         m_out.valid <= mmureq;
 285         m_out.iside <= v.instr_fault;
 286         m_out.load <= r.load;
 287         # m_out.priv <= r.priv_mode; TODO
 288         m_out.tlbie <= v.tlbie;
 289         # m_out.mtspr <= mmu_mtspr; # TODO
 290         # m_out.sprn <= sprn; # TODO
 291         m_out.addr <= maddr;
 292         # m_out.slbia <= l_in.insn(7); # TODO: no idea what this is
 293         # m_out.rs <= l_in.data; # nope, probably not needed, TODO investigate
 294         '''
 295
 296         return m
 297
 298     def ports(self):
 299         yield from super().ports()
 300         # TODO: memory ports
 301
 302
 303 class TestSRAMLoadStore1(LoadStore1):
 304     def __init__(self, pspec):
 305         super().__init__(pspec)
 306         pspec = self.pspec
 307         # small 32-entry Memory
 308         if (hasattr(pspec, "dmem_test_depth") and
 309                 isinstance(pspec.dmem_test_depth, int)):
 310             depth = pspec.dmem_test_depth
 311         else:
 312             depth = 32
 313         print("TestSRAMBareLoadStoreUnit depth", depth)
 314
 315         self.mem = Memory(width=pspec.reg_wid, depth=depth)
 316
 317     def elaborate(self, platform):
 318         m = super().elaborate(platform)
 319         comb = m.d.comb
 320         m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8,
 321                                         features={'cti', 'bte', 'err'})
 322         dbus = self.dbus
 323
 324         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
 325         # note: SRAM is a target (slave), dbus is initiator (master)
 326         fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
 327         fanins = ['dat_r', 'ack', 'err']
 328         for fanout in fanouts:
 329             print("fanout", fanout, getattr(sram.bus, fanout).shape(),
 330                   getattr(dbus, fanout).shape())
 331             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 332             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 333         for fanin in fanins:
 334             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
 335         # connect address
 336         comb += sram.bus.adr.eq(dbus.adr)
 337
 338         return m
 339