src/soc/fu/ldst/loadstore.py

   1 """LoadStore1 FSM.
   2
   3 based on microwatt loadstore1.vhdl, but conforming to PortInterface.
   4 unlike loadstore1.vhdl this does *not* deal with actual Load/Store
   5 ops: that job is handled by LDSTCompUnit, which talks to LoadStore1
   6 by way of PortInterface.  PortInterface is where things need extending,
   7 such as adding dcbz support, etc.
   8
   9 this module basically handles "pure" load / store operations, and
  10 its first job is to ask the D-Cache for the data.  if that fails,
  11 the second task (if virtual memory is enabled) is to ask the MMU
  12 to perform a TLB, then to go *back* to the cache and ask again.
  13
  14 Links:
  15
  16 * https://bugs.libre-soc.org/show_bug.cgi?id=465
  17
  18 """
  19
  20 from nmigen import (Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux,
  21                     Record, Memory,
  22                     Const)
  23 from nmutil.util import rising_edge
  24 from enum import Enum, unique
  25
  26 from soc.experiment.dcache import DCache
  27 from soc.experiment.pimem import PortInterfaceBase
  28 from soc.experiment.mem_types import LoadStore1ToMMUType
  29 from soc.experiment.mem_types import MMUToLoadStore1Type
  30
  31 from soc.minerva.wishbone import make_wb_layout
  32 from soc.bus.sram import SRAM
  33
  34
  35 @unique
  36 class State(Enum):
  37     IDLE = 0       # ready for instruction
  38     ACK_WAIT = 1   # waiting for ack from dcache
  39     MMU_LOOKUP = 2 # waiting for MMU to look up translation
  40     TLBIE_WAIT = 3 # waiting for MMU to finish doing a tlbie
  41     COMPLETE = 4   # extra cycle to complete an operation
  42
  43
  44 # glue logic for microwatt mmu and dcache
  45 class LoadStore1(PortInterfaceBase):
  46     def __init__(self, pspec):
  47         self.pspec = pspec
  48         self.disable_cache = (hasattr(pspec, "disable_cache") and
  49                               pspec.disable_cache == True)
  50         regwid = pspec.reg_wid
  51         addrwid = pspec.addr_wid
  52
  53         super().__init__(regwid, addrwid)
  54         self.dcache = DCache()
  55         # these names are from the perspective of here (LoadStore1)
  56         self.d_out  = self.dcache.d_in     # in to dcache is out for LoadStore
  57         self.d_in = self.dcache.d_out      # out from dcache is in for LoadStore
  58         self.m_out  = LoadStore1ToMMUType() # out *to* MMU
  59         self.m_in = MMUToLoadStore1Type()   # in *from* MMU
  60
  61         # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
  62         self.dbus = Record(make_wb_layout(pspec))
  63
  64         # for creating a single clock blip to DCache
  65         self.d_valid = Signal()
  66         self.d_w_valid = Signal()
  67         self.d_validblip = Signal()
  68
  69         # DSISR and DAR cached values.  note that the MMU FSM is where
  70         # these are accessed by OP_MTSPR/OP_MFSPR, on behalf of LoadStore1.
  71         # by contrast microwatt has the spr set/get done *in* loadstore1.vhdl
  72         self.dsisr = Signal(64)
  73         self.dar = Signal(64)
  74
  75         # state info for LD/ST
  76         self.done          = Signal()
  77         # latch most of the input request
  78         self.load          = Signal()
  79         self.tlbie         = Signal()
  80         self.dcbz          = Signal()
  81         self.addr          = Signal(64)
  82         self.store_data    = Signal(64)
  83         self.load_data     = Signal(64)
  84         self.byte_sel      = Signal(8)
  85         self.update        = Signal()
  86         #self.xerc         : xer_common_t;
  87         #self.reserve       = Signal()
  88         #self.atomic        = Signal()
  89         #self.atomic_last   = Signal()
  90         #self.rc            = Signal()
  91         self.nc            = Signal()              # non-cacheable access
  92         self.virt_mode     = Signal()
  93         self.priv_mode     = Signal()
  94         self.state        = Signal(State)
  95         self.instr_fault   = Signal()
  96         self.align_intr    = Signal()
  97         self.busy          = Signal()
  98         self.wait_dcache   = Signal()
  99         self.wait_mmu      = Signal()
 100         #self.mode_32bit    = Signal()
 101         self.wr_sel        = Signal(2)
 102         self.interrupt     = Signal()
 103         #self.intr_vec     : integer range 0 to 16#fff#;
 104         #self.nia           = Signal(64)
 105         #self.srr1          = Signal(16)
 106
 107     def set_wr_addr(self, m, addr, mask, misalign):
 108         m.d.comb += self.load.eq(0) # store operation
 109
 110         m.d.comb += self.d_out.load.eq(0)
 111         m.d.comb += self.byte_sel.eq(mask)
 112         m.d.comb += self.addr.eq(addr)
 113         m.d.comb += self.align_intr.eq(misalign)
 114         # option to disable the cache entirely for write
 115         if self.disable_cache:
 116             m.d.comb += self.nc.eq(1)
 117         return None
 118
 119     def set_rd_addr(self, m, addr, mask, misalign):
 120         m.d.comb += self.d_valid.eq(1)
 121         m.d.comb += self.d_out.valid.eq(self.d_validblip)
 122         m.d.comb += self.load.eq(1) # load operation
 123         m.d.comb += self.d_out.load.eq(1)
 124         m.d.comb += self.byte_sel.eq(mask)
 125         m.d.comb += self.align_intr.eq(misalign)
 126         m.d.comb += self.addr.eq(addr)
 127         # BAD HACK! disable cacheing on LD when address is 0xCxxx_xxxx
 128         # this is for peripherals. same thing done in Microwatt loadstore1.vhdl
 129         with m.If(addr[28:] == Const(0xc, 4)):
 130             m.d.comb += self.nc.eq(1)
 131         # option to disable the cache entirely for read
 132         if self.disable_cache:
 133             m.d.comb += self.nc.eq(1)
 134         return None #FIXME return value
 135
 136     def set_wr_data(self, m, data, wen):
 137         # do the "blip" on write data
 138         m.d.comb += self.d_valid.eq(1)
 139         m.d.comb += self.d_out.valid.eq(self.d_validblip)
 140         # put data into comb which is picked up in main elaborate()
 141         m.d.comb += self.d_w_valid.eq(1)
 142         m.d.comb += self.store_data.eq(data)
 143         #m.d.sync += self.d_out.byte_sel.eq(wen) # this might not be needed
 144         st_ok = self.done # TODO indicates write data is valid
 145         return st_ok
 146
 147     def get_rd_data(self, m):
 148         ld_ok = self.done     # indicates read data is valid
 149         data = self.load_data # actual read data
 150         return data, ld_ok
 151
 152     def elaborate(self, platform):
 153         m = super().elaborate(platform)
 154         comb, sync = m.d.comb, m.d.sync
 155
 156         # create dcache module
 157         m.submodules.dcache = dcache = self.dcache
 158
 159         # temp vars
 160         d_out, d_in, m_in, dbus = self.d_out, self.d_in, self.m_in, self.dbus
 161         exc = self.pi.exc_o
 162         exception = exc.happened
 163         mmureq = Signal()
 164
 165         # copy of address, but gets over-ridden for OP_FETCH_FAILED
 166         maddr = Signal(64)
 167         m.d.comb += maddr.eq(self.addr)
 168
 169         # create a blip (single pulse) on valid read/write request
 170         # this can be over-ridden in the FSM to get dcache to re-run
 171         # a request when MMU_LOOKUP completes
 172         m.d.comb += self.d_validblip.eq(rising_edge(m, self.d_valid))
 173
 174         # fsm skeleton
 175         with m.Switch(self.state):
 176             with m.Case(State.IDLE):
 177                 with m.If(self.d_validblip):
 178                     sync += self.state.eq(State.ACK_WAIT)
 179
 180             with m.Case(State.ACK_WAIT): # waiting for completion
 181                 with m.If(d_in.error):
 182                     with m.If(d_in.cache_paradox):
 183                         comb += exception.eq(1)
 184                         sync += self.state.eq(State.IDLE)
 185                         sync += self.dsisr[63 - 38].eq(~self.load)
 186                         # XXX there is no architected bit for this
 187                         # (probably should be a machine check in fact)
 188                         sync += self.dsisr[63 - 35].eq(d_in.cache_paradox)
 189
 190                     with m.Else():
 191                         # Look up the translation for TLB miss
 192                         # and also for permission error and RC error
 193                         # in case the PTE has been updated.
 194                         comb += self.mmureq.eq(1)
 195                         sync += self.state.eq(State.MMU_LOOKUP)
 196                 with m.If(d_in.valid):
 197                     m.d.comb += self.done.eq(1)
 198                     sync += self.state.eq(State.IDLE)
 199                     with m.If(self.load):
 200                         m.d.comb += self.load_data.eq(d_in.data)
 201
 202             with m.Case(State.MMU_LOOKUP):
 203                 with m.If(m_in.done):
 204                     with m.If(~self.instr_fault):
 205                         # retry the request now that the MMU has
 206                         # installed a TLB entry
 207                         m.d.comb += self.d_validblip.eq(1) # re-run dcache req
 208                         sync += self.state.eq(State.ACK_WAIT)
 209                 with m.If(m_in.err):
 210                     comb += exception.eq(1)
 211                     sync += self.dsisr[63 - 33].eq(m_in.invalid)
 212                     sync += self.dsisr[63 - 36].eq(m_in.perm_error)
 213                     sync += self.dsisr[63 - 38].eq(self.load)
 214                     sync += self.dsisr[63 - 44].eq(m_in.badtree)
 215                     sync += self.dsisr[63 - 45].eq(m_in.rc_error)
 216
 217                 '''
 218                 if m_in.done = '1' then # actually m_in.done
 219                     if r.instr_fault = '0' then
 220                         # retry the request now that the MMU has
 221                         # installed a TLB entry
 222                         v.state := ACK_WAIT;
 223                     end if;
 224                 end if;
 225                 if m_in.err = '1' then # actually m_in.err
 226                     dsisr(63 - 33) := m_in.invalid;
 227                     dsisr(63 - 36) := m_in.perm_error;
 228                     dsisr(63 - 38) := not r.load;
 229                     dsisr(63 - 44) := m_in.badtree;
 230                     dsisr(63 - 45) := m_in.rc_error;
 231                 end if;
 232                 '''
 233                 pass
 234
 235             with m.Case(State.TLBIE_WAIT):
 236                 pass
 237             with m.Case(State.COMPLETE):
 238                 pass
 239
 240         # happened, alignment, instr_fault, invalid.
 241         # note that all of these flow through - eventually to the TRAP
 242         # pipeline, via PowerDecoder2.
 243         with m.If(self.align_intr):
 244             comb += exc.happened.eq(1)
 245         comb += exc.invalid.eq(m_in.invalid)
 246         comb += exc.alignment.eq(self.align_intr)
 247         # badtree, perm_error, rc_error, segment_fault
 248         comb += exc.badtree.eq(m_in.badtree)
 249         comb += exc.perm_error.eq(m_in.perm_error)
 250         comb += exc.rc_error.eq(m_in.rc_error)
 251         comb += exc.segment_fault.eq(m_in.segerr)
 252
 253         # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
 254         comb += dbus.adr.eq(dcache.wb_out.adr)
 255         comb += dbus.dat_w.eq(dcache.wb_out.dat)
 256         comb += dbus.sel.eq(dcache.wb_out.sel)
 257         comb += dbus.cyc.eq(dcache.wb_out.cyc)
 258         comb += dbus.stb.eq(dcache.wb_out.stb)
 259         comb += dbus.we.eq(dcache.wb_out.we)
 260
 261         comb += dcache.wb_in.dat.eq(dbus.dat_r)
 262         comb += dcache.wb_in.ack.eq(dbus.ack)
 263         if hasattr(dbus, "stall"):
 264             comb += dcache.wb_in.stall.eq(dbus.stall)
 265
 266         # write out d data only when flag set
 267         with m.If(self.d_w_valid):
 268             m.d.sync += d_out.data.eq(self.store_data)
 269         with m.Else():
 270             m.d.sync += d_out.data.eq(0)
 271
 272         # this must move into the FSM, conditionally noticing that
 273         # the "blip" comes from self.d_validblip.
 274         # task 1: look up in dcache
 275         # task 2: if dcache fails, look up in MMU.
 276         # do **NOT** confuse the two.
 277         m.d.comb += d_out.load.eq(self.load)
 278         m.d.comb += d_out.byte_sel.eq(self.byte_sel)
 279         m.d.comb += d_out.addr.eq(self.addr)
 280         m.d.comb += d_out.nc.eq(self.nc)
 281
 282         # XXX these should be possible to remove but for some reason
 283         # cannot be... yet. TODO, investigate
 284         m.d.comb += self.done.eq(d_in.valid)
 285         m.d.comb += self.load_data.eq(d_in.data)
 286
 287         ''' TODO: translate to nmigen.
 288         -- Update outputs to MMU
 289         m_out.valid <= mmureq;
 290         m_out.iside <= v.instr_fault;
 291         m_out.load <= r.load;
 292         # m_out.priv <= r.priv_mode; TODO
 293         m_out.tlbie <= v.tlbie;
 294         # m_out.mtspr <= mmu_mtspr; # TODO
 295         # m_out.sprn <= sprn; # TODO
 296         m_out.addr <= maddr;
 297         # m_out.slbia <= l_in.insn(7); # TODO: no idea what this is
 298         # m_out.rs <= l_in.data; # nope, probably not needed, TODO investigate
 299         '''
 300
 301         return m
 302
 303     def ports(self):
 304         yield from super().ports()
 305         # TODO: memory ports
 306
 307
 308 class TestSRAMLoadStore1(LoadStore1):
 309     def __init__(self, pspec):
 310         super().__init__(pspec)
 311         pspec = self.pspec
 312         # small 32-entry Memory
 313         if (hasattr(pspec, "dmem_test_depth") and
 314                 isinstance(pspec.dmem_test_depth, int)):
 315             depth = pspec.dmem_test_depth
 316         else:
 317             depth = 32
 318         print("TestSRAMBareLoadStoreUnit depth", depth)
 319
 320         self.mem = Memory(width=pspec.reg_wid, depth=depth)
 321
 322     def elaborate(self, platform):
 323         m = super().elaborate(platform)
 324         comb = m.d.comb
 325         m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8,
 326                                         features={'cti', 'bte', 'err'})
 327         dbus = self.dbus
 328
 329         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
 330         # note: SRAM is a target (slave), dbus is initiator (master)
 331         fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
 332         fanins = ['dat_r', 'ack', 'err']
 333         for fanout in fanouts:
 334             print("fanout", fanout, getattr(sram.bus, fanout).shape(),
 335                   getattr(dbus, fanout).shape())
 336             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 337             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 338         for fanin in fanins:
 339             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
 340         # connect address
 341         comb += sram.bus.adr.eq(dbus.adr)
 342
 343         return m
 344