src/soc/fu/ldst/loadstore.py

   1 """LoadStore1 FSM.
   2
   3 based on microwatt loadstore1.vhdl, but conforming to PortInterface.
   4 unlike loadstore1.vhdl this does *not* deal with actual Load/Store
   5 ops: that job is handled by LDSTCompUnit, which talks to LoadStore1
   6 by way of PortInterface.  PortInterface is where things need extending,
   7 such as adding dcbz support, etc.
   8
   9 this module basically handles "pure" load / store operations, and
  10 its first job is to ask the D-Cache for the data.  if that fails,
  11 the second task (if virtual memory is enabled) is to ask the MMU
  12 to perform a TLB, then to go *back* to the cache and ask again.
  13
  14 Links:
  15
  16 * https://bugs.libre-soc.org/show_bug.cgi?id=465
  17
  18 """
  19
  20 from nmigen import (Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux,
  21                     Record, Memory,
  22                     Const)
  23 from nmutil.iocontrol import RecordObject
  24 from nmutil.util import rising_edge, Display
  25 from enum import Enum, unique
  26
  27 from soc.experiment.dcache import DCache
  28 from soc.experiment.pimem import PortInterfaceBase
  29 from soc.experiment.mem_types import LoadStore1ToMMUType
  30 from soc.experiment.mem_types import MMUToLoadStore1Type
  31
  32 from soc.minerva.wishbone import make_wb_layout
  33 from soc.bus.sram import SRAM
  34 from nmutil.util import Display
  35
  36
  37 @unique
  38 class State(Enum):
  39     IDLE = 0       # ready for instruction
  40     ACK_WAIT = 1   # waiting for ack from dcache
  41     MMU_LOOKUP = 2 # waiting for MMU to look up translation
  42     TLBIE_WAIT = 3 # waiting for MMU to finish doing a tlbie
  43
  44
  45 # captures the LDSTRequest from the PortInterface, which "blips" most
  46 # of this at us (pipeline-style).
  47 class LDSTRequest(RecordObject):
  48     def __init__(self, name=None):
  49         RecordObject.__init__(self, name=name)
  50
  51         self.load          = Signal()
  52         self.dcbz          = Signal()
  53         self.addr          = Signal(64)
  54         # self.store_data    = Signal(64) # this is already sync (on a delay)
  55         self.byte_sel      = Signal(8)
  56         self.nc            = Signal()              # non-cacheable access
  57         self.virt_mode     = Signal()
  58         self.priv_mode     = Signal()
  59         self.align_intr    = Signal()
  60
  61 # glue logic for microwatt mmu and dcache
  62 class LoadStore1(PortInterfaceBase):
  63     def __init__(self, pspec):
  64         self.pspec = pspec
  65         self.disable_cache = (hasattr(pspec, "disable_cache") and
  66                               pspec.disable_cache == True)
  67         regwid = pspec.reg_wid
  68         addrwid = pspec.addr_wid
  69
  70         super().__init__(regwid, addrwid)
  71         self.dcache = DCache()
  72         # these names are from the perspective of here (LoadStore1)
  73         self.d_out  = self.dcache.d_in     # in to dcache is out for LoadStore
  74         self.d_in = self.dcache.d_out      # out from dcache is in for LoadStore
  75         self.m_out  = LoadStore1ToMMUType() # out *to* MMU
  76         self.m_in = MMUToLoadStore1Type()   # in *from* MMU
  77         self.req = LDSTRequest(name="ldst_req")
  78
  79         # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
  80         self.dbus = Record(make_wb_layout(pspec))
  81
  82         # for creating a single clock blip to DCache
  83         self.d_valid = Signal()
  84         self.d_w_valid = Signal()
  85         self.d_validblip = Signal()
  86
  87         # DSISR and DAR cached values.  note that the MMU FSM is where
  88         # these are accessed by OP_MTSPR/OP_MFSPR, on behalf of LoadStore1.
  89         # by contrast microwatt has the spr set/get done *in* loadstore1.vhdl
  90         self.dsisr = Signal(64)
  91         #self.dar = Signal(64)
  92
  93         # state info for LD/ST
  94         self.done          = Signal()
  95         # latch most of the input request
  96         self.load          = Signal()
  97         self.tlbie         = Signal()
  98         self.dcbz          = Signal()
  99         self.addr          = Signal(64)
 100         self.store_data    = Signal(64)
 101         self.load_data     = Signal(64)
 102         self.byte_sel      = Signal(8)
 103         #self.xerc         : xer_common_t;
 104         #self.reserve       = Signal()
 105         #self.atomic        = Signal()
 106         #self.atomic_last   = Signal()
 107         #self.rc            = Signal()
 108         self.nc            = Signal()              # non-cacheable access
 109         self.virt_mode     = Signal()
 110         self.priv_mode     = Signal()
 111         self.state        = Signal(State)
 112         self.instr_fault   = Signal()
 113         self.align_intr    = Signal()
 114         self.busy          = Signal()
 115         self.wait_dcache   = Signal()
 116         self.wait_mmu      = Signal()
 117         #self.mode_32bit    = Signal()
 118         #self.intr_vec     : integer range 0 to 16#fff#;
 119         #self.nia           = Signal(64)
 120         #self.srr1          = Signal(16)
 121
 122     def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz):
 123         m.d.comb += self.req.load.eq(0) # store operation
 124         m.d.comb += self.req.byte_sel.eq(mask)
 125         m.d.comb += self.req.addr.eq(addr)
 126         m.d.comb += self.req.priv_mode.eq(~msr_pr) # not-problem  ==> priv
 127         m.d.comb += self.req.virt_mode.eq(msr_pr) # problem-state ==> virt
 128         m.d.comb += self.req.align_intr.eq(misalign)
 129         m.d.comb += self.req.dcbz.eq(is_dcbz)
 130
 131         # m.d.comb += Display("set_wr_addr %i dcbz %i",addr,is_dcbz)
 132
 133         # option to disable the cache entirely for write
 134         if self.disable_cache:
 135             m.d.comb += self.req.nc.eq(1)
 136         return None
 137
 138     def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
 139         m.d.comb += self.d_valid.eq(1)
 140         m.d.comb += self.req.load.eq(1) # load operation
 141         m.d.comb += self.req.byte_sel.eq(mask)
 142         m.d.comb += self.req.align_intr.eq(misalign)
 143         m.d.comb += self.req.addr.eq(addr)
 144         m.d.comb += self.req.priv_mode.eq(~msr_pr) # not-problem  ==> priv
 145         m.d.comb += self.req.virt_mode.eq(msr_pr) # problem-state ==> virt
 146         # BAD HACK! disable cacheing on LD when address is 0xCxxx_xxxx
 147         # this is for peripherals. same thing done in Microwatt loadstore1.vhdl
 148         with m.If(addr[28:] == Const(0xc, 4)):
 149             m.d.comb += self.req.nc.eq(1)
 150         # option to disable the cache entirely for read
 151         if self.disable_cache:
 152             m.d.comb += self.req.nc.eq(1)
 153         return None #FIXME return value
 154
 155     def set_wr_data(self, m, data, wen):
 156         # do the "blip" on write data
 157         m.d.comb += self.d_valid.eq(1)
 158         # put data into comb which is picked up in main elaborate()
 159         m.d.comb += self.d_w_valid.eq(1)
 160         m.d.comb += self.store_data.eq(data)
 161         #m.d.sync += self.d_out.byte_sel.eq(wen) # this might not be needed
 162         st_ok = self.done # TODO indicates write data is valid
 163         return st_ok
 164
 165     def get_rd_data(self, m):
 166         ld_ok = self.done     # indicates read data is valid
 167         data = self.load_data # actual read data
 168         return data, ld_ok
 169
 170     def elaborate(self, platform):
 171         m = super().elaborate(platform)
 172         comb, sync = m.d.comb, m.d.sync
 173
 174         # create dcache module
 175         m.submodules.dcache = dcache = self.dcache
 176
 177         # temp vars
 178         d_out, d_in, dbus = self.d_out, self.d_in, self.dbus
 179         m_out, m_in = self.m_out, self.m_in
 180         exc = self.pi.exc_o
 181         exception = exc.happened
 182         mmureq = Signal()
 183
 184         # copy of address, but gets over-ridden for OP_FETCH_FAILED
 185         maddr = Signal(64)
 186         m.d.comb += maddr.eq(self.addr)
 187
 188         # create a blip (single pulse) on valid read/write request
 189         # this can be over-ridden in the FSM to get dcache to re-run
 190         # a request when MMU_LOOKUP completes.
 191         m.d.comb += self.d_validblip.eq(rising_edge(m, self.d_valid))
 192         ldst_r = LDSTRequest("ldst_r")
 193
 194         comb += Display("MMUTEST: LoadStore1 d_in.error=%i",d_in.error)
 195
 196         # fsm skeleton
 197         with m.Switch(self.state):
 198             with m.Case(State.IDLE):
 199                 with m.If(self.d_validblip & ~exc.happened):
 200                     comb += self.busy.eq(1)
 201                     sync += self.state.eq(State.ACK_WAIT)
 202                     sync += ldst_r.eq(self.req) # copy of LDSTRequest on "blip"
 203 #                   sync += Display("validblip self.req.virt_mode=%i",
 204 #                   self.req.virt_mode)
 205                 with m.Else():
 206                     sync += ldst_r.eq(0)
 207
 208             # waiting for completion
 209             with m.Case(State.ACK_WAIT):
 210                 comb += Display("MMUTEST: ACK_WAIT")
 211                 comb += self.busy.eq(~exc.happened)
 212
 213                 with m.If(d_in.error):
 214                     # cache error is not necessarily "final", it could
 215                     # be that it was just a TLB miss
 216                     with m.If(d_in.cache_paradox):
 217                         comb += exception.eq(1)
 218                         sync += self.state.eq(State.IDLE)
 219                         sync += ldst_r.eq(0)
 220                         sync += Display("cache error -> update dsisr")
 221                         sync += self.dsisr[63 - 38].eq(~self.load)
 222                         # XXX there is no architected bit for this
 223                         # (probably should be a machine check in fact)
 224                         sync += self.dsisr[63 - 35].eq(d_in.cache_paradox)
 225
 226                     with m.Else():
 227                         # Look up the translation for TLB miss
 228                         # and also for permission error and RC error
 229                         # in case the PTE has been updated.
 230                         comb += mmureq.eq(1)
 231                         sync += self.state.eq(State.MMU_LOOKUP)
 232                 with m.If(d_in.valid):
 233                     m.d.comb += self.done.eq(~mmureq) # done if not doing MMU
 234                     with m.If(self.done):
 235                         sync += Display("ACK_WAIT, done %x", self.addr)
 236                     sync += self.state.eq(State.IDLE)
 237                     sync += ldst_r.eq(0)
 238                     with m.If(self.load):
 239                         m.d.comb += self.load_data.eq(d_in.data)
 240
 241             # waiting here for the MMU TLB lookup to complete.
 242             # either re-try the dcache lookup or throw MMU exception
 243             with m.Case(State.MMU_LOOKUP):
 244                 comb += Display("MMUTEST: MMU_LOOKUP")
 245                 comb += self.busy.eq(1)
 246                 with m.If(m_in.done):
 247                     with m.If(~self.instr_fault):
 248                         sync += Display("MMU_LOOKUP, done %x -> %x",
 249                                         self.addr, d_out.addr)
 250                         # retry the request now that the MMU has
 251                         # installed a TLB entry, if not exception raised
 252                         m.d.comb += self.d_out.valid.eq(~exception)
 253                         sync += self.state.eq(State.ACK_WAIT)
 254                         sync += ldst_r.eq(0)
 255                     with m.Else():
 256                         sync += Display("MMU_LOOKUP, exception %x", self.addr)
 257                         # instruction lookup fault: store address in DAR
 258                         comb += exc.happened.eq(1) # reason = MMU_LOOKUP
 259                         # mark dar as updated ?
 260                         sync += self.pi.dar_o.eq(self.addr)
 261
 262                 with m.If(m_in.err):
 263                     # MMU RADIX exception thrown
 264                     comb += exception.eq(1)
 265                     sync += Display("MMU RADIX exception thrown")
 266                     sync += self.dsisr[63 - 33].eq(m_in.invalid)
 267                     sync += self.dsisr[63 - 36].eq(m_in.perm_error)
 268                     sync += self.dsisr[63 - 38].eq(self.load)
 269                     sync += self.dsisr[63 - 44].eq(m_in.badtree)
 270                     sync += self.dsisr[63 - 45].eq(m_in.rc_error)
 271
 272             with m.Case(State.TLBIE_WAIT):
 273                 pass
 274
 275         # alignment error: store address in DAR
 276         with m.If(self.align_intr):
 277             comb += exc.happened.eq(1) # reason = alignment
 278             sync += Display("alignment error: store addr in DAR %x", self.addr)
 279             sync += self.pi.dar_o.eq(self.addr)
 280             # TODO report reason
 281
 282         # happened, alignment, instr_fault, invalid.
 283         # note that all of these flow through - eventually to the TRAP
 284         # pipeline, via PowerDecoder2.
 285         comb += exc.invalid.eq(m_in.invalid)
 286         comb += exc.alignment.eq(self.align_intr)
 287         comb += exc.instr_fault.eq(self.instr_fault)
 288         # badtree, perm_error, rc_error, segment_fault
 289         comb += exc.badtree.eq(m_in.badtree)
 290         comb += exc.perm_error.eq(m_in.perm_error)
 291         comb += exc.rc_error.eq(m_in.rc_error)
 292         comb += exc.segment_fault.eq(m_in.segerr)
 293
 294         # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
 295         comb += dbus.adr.eq(dcache.wb_out.adr)
 296         comb += dbus.dat_w.eq(dcache.wb_out.dat)
 297         comb += dbus.sel.eq(dcache.wb_out.sel)
 298         comb += dbus.cyc.eq(dcache.wb_out.cyc)
 299         comb += dbus.stb.eq(dcache.wb_out.stb)
 300         comb += dbus.we.eq(dcache.wb_out.we)
 301
 302         comb += dcache.wb_in.dat.eq(dbus.dat_r)
 303         comb += dcache.wb_in.ack.eq(dbus.ack)
 304         if hasattr(dbus, "stall"):
 305             comb += dcache.wb_in.stall.eq(dbus.stall)
 306
 307         # update out d data when flag set
 308         with m.If(self.d_w_valid):
 309             m.d.sync += d_out.data.eq(self.store_data)
 310         #with m.Else():
 311         #    m.d.sync += d_out.data.eq(0)
 312         # unit test passes with that change
 313
 314         # this must move into the FSM, conditionally noticing that
 315         # the "blip" comes from self.d_validblip.
 316         # task 1: look up in dcache
 317         # task 2: if dcache fails, look up in MMU.
 318         # do **NOT** confuse the two.
 319         with m.If(self.d_validblip):
 320             m.d.comb += self.d_out.valid.eq(~exc.happened)
 321             m.d.comb += d_out.load.eq(self.req.load)
 322             m.d.comb += d_out.byte_sel.eq(self.req.byte_sel)
 323             m.d.comb += self.addr.eq(self.req.addr)
 324             m.d.comb += d_out.nc.eq(self.req.nc)
 325             m.d.comb += d_out.priv_mode.eq(self.req.priv_mode)
 326             m.d.comb += d_out.virt_mode.eq(self.req.virt_mode)
 327             m.d.comb += self.align_intr.eq(self.req.align_intr)
 328             #m.d.comb += Display("validblip dcbz=%i addr=%x",
 329             #self.req.dcbz,self.req.addr)
 330             m.d.comb += d_out.dcbz.eq(self.req.dcbz)
 331         with m.Else():
 332             m.d.comb += d_out.load.eq(ldst_r.load)
 333             m.d.comb += d_out.byte_sel.eq(ldst_r.byte_sel)
 334             m.d.comb += self.addr.eq(ldst_r.addr)
 335             m.d.comb += d_out.nc.eq(ldst_r.nc)
 336             m.d.comb += d_out.priv_mode.eq(ldst_r.priv_mode)
 337             m.d.comb += d_out.virt_mode.eq(ldst_r.virt_mode)
 338             m.d.comb += self.align_intr.eq(ldst_r.align_intr)
 339             #m.d.comb += Display("no_validblip dcbz=%i addr=%x",
 340             #ldst_r.dcbz,ldst_r.addr)
 341             m.d.comb += d_out.dcbz.eq(ldst_r.dcbz)
 342
 343         # XXX these should be possible to remove but for some reason
 344         # cannot be... yet. TODO, investigate
 345         m.d.comb += self.load_data.eq(d_in.data)
 346         m.d.comb += d_out.addr.eq(self.addr)
 347
 348         # Update outputs to MMU
 349         m.d.comb += m_out.valid.eq(mmureq)
 350         m.d.comb += m_out.iside.eq(self.instr_fault)
 351         m.d.comb += m_out.load.eq(ldst_r.load)
 352         # m_out.priv <= r.priv_mode; TODO
 353         m.d.comb += m_out.tlbie.eq(self.tlbie)
 354         # m_out.mtspr <= mmu_mtspr; # TODO
 355         # m_out.sprn <= sprn; # TODO
 356         m.d.comb += m_out.addr.eq(maddr)
 357         # m_out.slbia <= l_in.insn(7); # TODO: no idea what this is
 358         # m_out.rs <= l_in.data; # nope, probably not needed, TODO investigate
 359
 360         return m
 361
 362     def ports(self):
 363         yield from super().ports()
 364         # TODO: memory ports
 365
 366
 367 class TestSRAMLoadStore1(LoadStore1):
 368     def __init__(self, pspec):
 369         super().__init__(pspec)
 370         pspec = self.pspec
 371         # small 32-entry Memory
 372         if (hasattr(pspec, "dmem_test_depth") and
 373                 isinstance(pspec.dmem_test_depth, int)):
 374             depth = pspec.dmem_test_depth
 375         else:
 376             depth = 32
 377         print("TestSRAMBareLoadStoreUnit depth", depth)
 378
 379         self.mem = Memory(width=pspec.reg_wid, depth=depth)
 380
 381     def elaborate(self, platform):
 382         m = super().elaborate(platform)
 383         comb = m.d.comb
 384         m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8,
 385                                         features={'cti', 'bte', 'err'})
 386         dbus = self.dbus
 387
 388         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
 389         # note: SRAM is a target (slave), dbus is initiator (master)
 390         fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
 391         fanins = ['dat_r', 'ack', 'err']
 392         for fanout in fanouts:
 393             print("fanout", fanout, getattr(sram.bus, fanout).shape(),
 394                   getattr(dbus, fanout).shape())
 395             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 396             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 397         for fanin in fanins:
 398             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
 399         # connect address
 400         comb += sram.bus.adr.eq(dbus.adr)
 401
 402         return m
 403