src/soc/fu/ldst/loadstore.py

   1 """LoadStore1 FSM.
   2
   3 based on microwatt loadstore1.vhdl
   4
   5 Links:
   6
   7 * https://bugs.libre-soc.org/show_bug.cgi?id=465
   8
   9 """
  10
  11 from nmigen import (Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux,
  12                     Record, Memory,
  13                     Const)
  14 from nmutil.util import rising_edge
  15 from enum import Enum, unique
  16
  17 from soc.experiment.dcache import DCache
  18 from soc.experiment.pimem import PortInterfaceBase
  19 from soc.experiment.mem_types import LoadStore1ToMMUType
  20 from soc.experiment.mem_types import MMUToLoadStore1Type
  21
  22 from soc.minerva.wishbone import make_wb_layout
  23 from soc.bus.sram import SRAM
  24
  25
  26 @unique
  27 class State(Enum):
  28     IDLE = 0       # ready for instruction
  29     ACK_WAIT = 1   # waiting for ack from dcache
  30     MMU_LOOKUP = 2 # waiting for MMU to look up translation
  31     TLBIE_WAIT = 3 # waiting for MMU to finish doing a tlbie
  32     FINISH_LFS = 4 # write back converted SP data for lfs*
  33     COMPLETE = 5   # extra cycle to complete an operation
  34
  35
  36 # glue logic for microwatt mmu and dcache
  37 class LoadStore1(PortInterfaceBase):
  38     def __init__(self, pspec):
  39         self.pspec = pspec
  40         self.disable_cache = (hasattr(pspec, "disable_cache") and
  41                               pspec.disable_cache == True)
  42         regwid = pspec.reg_wid
  43         addrwid = pspec.addr_wid
  44
  45         super().__init__(regwid, addrwid)
  46         self.dcache = DCache()
  47         self.d_in  = self.dcache.d_in
  48         self.d_out = self.dcache.d_out
  49         self.l_in  = LoadStore1ToMMUType()
  50         self.l_out = MMUToLoadStore1Type()
  51         # TODO microwatt
  52         self.mmureq = Signal()
  53         self.derror = Signal()
  54
  55         # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
  56         self.dbus = Record(make_wb_layout(pspec))
  57
  58         # for creating a single clock blip to DCache
  59         self.d_valid = Signal()
  60         self.d_w_valid = Signal()
  61         self.d_validblip = Signal()
  62
  63         # DSISR and DAR cached values.  note that the MMU FSM is where
  64         # these are accessed by OP_MTSPR/OP_MFSPR, on behalf of LoadStore1.
  65         # by contrast microwatt has the spr set/get done *in* loadstore1.vhdl
  66         self.dsisr = Signal(64)
  67         self.dar = Signal(64)
  68
  69         # state info for LD/ST
  70         self.done          = Signal()
  71         # latch most of the input request
  72         self.load          = Signal()
  73         self.tlbie         = Signal()
  74         self.dcbz          = Signal()
  75         self.addr          = Signal(64)
  76         self.store_data    = Signal(64)
  77         self.load_data     = Signal(64)
  78         self.byte_sel      = Signal(8)
  79         self.update        = Signal()
  80         #self.xerc         : xer_common_t;
  81         #self.reserve       = Signal()
  82         #self.atomic        = Signal()
  83         #self.atomic_last   = Signal()
  84         #self.rc            = Signal()
  85         self.nc            = Signal()              # non-cacheable access
  86         self.virt_mode     = Signal()
  87         self.priv_mode     = Signal()
  88         self.state        = Signal(State)
  89         self.instr_fault   = Signal()
  90         self.align_intr    = Signal()
  91         self.busy          = Signal()
  92         self.wait_dcache   = Signal()
  93         self.wait_mmu      = Signal()
  94         #self.mode_32bit    = Signal()
  95         self.wr_sel        = Signal(2)
  96         self.interrupt     = Signal()
  97         #self.intr_vec     : integer range 0 to 16#fff#;
  98         #self.nia           = Signal(64)
  99         #self.srr1          = Signal(16)
 100
 101     def set_wr_addr(self, m, addr, mask, misalign):
 102         m.d.comb += self.load.eq(0) # store operation
 103
 104         m.d.comb += self.d_in.load.eq(0)
 105         m.d.comb += self.byte_sel.eq(mask)
 106         m.d.comb += self.addr.eq(addr)
 107         m.d.comb += self.align_intr.eq(misalign)
 108         # option to disable the cache entirely for write
 109         if self.disable_cache:
 110             m.d.comb += self.nc.eq(1)
 111         return None
 112
 113     def set_rd_addr(self, m, addr, mask, misalign):
 114         m.d.comb += self.d_valid.eq(1)
 115         m.d.comb += self.d_in.valid.eq(self.d_validblip)
 116         m.d.comb += self.load.eq(1) # load operation
 117         m.d.comb += self.d_in.load.eq(1)
 118         m.d.comb += self.byte_sel.eq(mask)
 119         m.d.comb += self.align_intr.eq(misalign)
 120         m.d.comb += self.addr.eq(addr)
 121         # BAD HACK! disable cacheing on LD when address is 0xCxxx_xxxx
 122         # this is for peripherals. same thing done in Microwatt loadstore1.vhdl
 123         with m.If(addr[28:] == Const(0xc, 4)):
 124             m.d.comb += self.nc.eq(1)
 125         # option to disable the cache entirely for read
 126         if self.disable_cache:
 127             m.d.comb += self.nc.eq(1)
 128         return None #FIXME return value
 129
 130     def set_wr_data(self, m, data, wen):
 131         # do the "blip" on write data
 132         m.d.comb += self.d_valid.eq(1)
 133         m.d.comb += self.d_in.valid.eq(self.d_validblip)
 134         # put data into comb which is picked up in main elaborate()
 135         m.d.comb += self.d_w_valid.eq(1)
 136         m.d.comb += self.store_data.eq(data)
 137         #m.d.sync += self.d_in.byte_sel.eq(wen) # this might not be needed
 138         st_ok = self.done # TODO indicates write data is valid
 139         return st_ok
 140
 141     def get_rd_data(self, m):
 142         ld_ok = self.done     # indicates read data is valid
 143         data = self.load_data # actual read data
 144         return data, ld_ok
 145
 146     """
 147     if d_in.error = '1' then
 148                 if d_in.cache_paradox = '1' then
 149                     -- signal an interrupt straight away
 150                     exception := '1';
 151                     dsisr(63 - 38) := not r2.req.load;
 152                     -- XXX there is no architected bit for this
 153                     -- (probably should be a machine check in fact)
 154                     dsisr(63 - 35) := d_in.cache_paradox;
 155                 else
 156                     -- Look up the translation for TLB miss
 157                     -- and also for permission error and RC error
 158                     -- in case the PTE has been updated.
 159                     mmureq := '1';
 160                     v.state := MMU_LOOKUP;
 161                     v.stage1_en := '0';
 162                 end if;
 163             end if;
 164     """
 165
 166     def elaborate(self, platform):
 167         m = super().elaborate(platform)
 168         comb, sync = m.d.comb, m.d.sync
 169
 170         # create dcache module
 171         m.submodules.dcache = dcache = self.dcache
 172
 173         # temp vars
 174         d_in, d_out, l_out, dbus = self.d_in, self.d_out, self.l_out, self.dbus
 175
 176         # fsm skeleton
 177         with m.Switch(self.state):
 178             with m.Case(State.IDLE):
 179                 pass
 180             with m.Case(State.SECOND_REQ):
 181                 # req.eq(1);
 182                 # v.state.eq(ACK_WAIT)
 183                 # v.last_dword.eq(0);
 184                 pass
 185             with m.Case(State.ACK_WAIT):
 186                 pass
 187             with m.Case(State.MMU_LOOKUP):
 188                 pass
 189             with m.Case(State.TLBIE_WAIT):
 190                 pass
 191             with m.Case(State.FINISH_LFS):
 192                 pass
 193             with m.Case(State.COMPLETE):
 194                 pass
 195         # microwatt: only if State.ACK_WAIZ
 196         with m.If(d_out.error):
 197             with m.If(d_out.cache_paradox):
 198                 sync += self.derror.eq(1)
 199                 sync += self.dsisr[63 - 38].eq(~self.load)
 200                 # XXX there is no architected bit for this
 201                 # (probably should be a machine check in fact)
 202                 sync += self.dsisr[63 - 35].eq(d_out.cache_paradox)
 203
 204             with m.Else():
 205                 # Look up the translation for TLB miss
 206                 # and also for permission error and RC error
 207                 # in case the PTE has been updated.
 208                 sync += self.mmureq.eq(1)
 209                 sync += self.state.eq(State.MMU_LOOKUP)
 210
 211         exc = self.pi.exc_o
 212
 213         # happened, alignment, instr_fault, invalid.
 214         # note that all of these flow through - eventually to the TRAP
 215         # pipeline, via PowerDecoder2.
 216         comb += exc.happened.eq(d_out.error | l_out.err | self.align_intr)
 217         comb += exc.invalid.eq(l_out.invalid)
 218         comb += exc.alignment.eq(self.align_intr)
 219
 220         # badtree, perm_error, rc_error, segment_fault
 221         comb += exc.badtree.eq(l_out.badtree)
 222         comb += exc.perm_error.eq(l_out.perm_error)
 223         comb += exc.rc_error.eq(l_out.rc_error)
 224         comb += exc.segment_fault.eq(l_out.segerr)
 225
 226         # TODO some exceptions set SPRs
 227
 228         # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
 229         comb += dbus.adr.eq(dcache.wb_out.adr)
 230         comb += dbus.dat_w.eq(dcache.wb_out.dat)
 231         comb += dbus.sel.eq(dcache.wb_out.sel)
 232         comb += dbus.cyc.eq(dcache.wb_out.cyc)
 233         comb += dbus.stb.eq(dcache.wb_out.stb)
 234         comb += dbus.we.eq(dcache.wb_out.we)
 235
 236         comb += dcache.wb_in.dat.eq(dbus.dat_r)
 237         comb += dcache.wb_in.ack.eq(dbus.ack)
 238         if hasattr(dbus, "stall"):
 239             comb += dcache.wb_in.stall.eq(dbus.stall)
 240
 241         # create a blip (single pulse) on valid read/write request
 242         m.d.comb += self.d_validblip.eq(rising_edge(m, self.d_valid))
 243
 244         # write out d data only when flag set
 245         with m.If(self.d_w_valid):
 246             m.d.sync += d_in.data.eq(self.store_data)
 247         with m.Else():
 248             m.d.sync += d_in.data.eq(0)
 249
 250         m.d.comb += d_in.load.eq(self.load)
 251         m.d.comb += d_in.byte_sel.eq(self.byte_sel)
 252         m.d.comb += d_in.addr.eq(self.addr)
 253         m.d.comb += d_in.nc.eq(self.nc)
 254         m.d.comb += d_in.valid.eq(self.mmureq)
 255         m.d.comb += self.done.eq(d_out.valid)
 256         m.d.comb += self.load_data.eq(d_out.data)
 257
 258         return m
 259
 260     def ports(self):
 261         yield from super().ports()
 262         # TODO: memory ports
 263
 264
 265 class TestSRAMLoadStore1(LoadStore1):
 266     def __init__(self, pspec):
 267         super().__init__(pspec)
 268         pspec = self.pspec
 269         # small 32-entry Memory
 270         if (hasattr(pspec, "dmem_test_depth") and
 271                 isinstance(pspec.dmem_test_depth, int)):
 272             depth = pspec.dmem_test_depth
 273         else:
 274             depth = 32
 275         print("TestSRAMBareLoadStoreUnit depth", depth)
 276
 277         self.mem = Memory(width=pspec.reg_wid, depth=depth)
 278
 279     def elaborate(self, platform):
 280         m = super().elaborate(platform)
 281         comb = m.d.comb
 282         m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8,
 283                                         features={'cti', 'bte', 'err'})
 284         dbus = self.dbus
 285
 286         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
 287         # note: SRAM is a target (slave), dbus is initiator (master)
 288         fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
 289         fanins = ['dat_r', 'ack', 'err']
 290         for fanout in fanouts:
 291             print("fanout", fanout, getattr(sram.bus, fanout).shape(),
 292                   getattr(dbus, fanout).shape())
 293             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 294             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 295         for fanin in fanins:
 296             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
 297         # connect address
 298         comb += sram.bus.adr.eq(dbus.adr)
 299
 300         return m
 301