1 from nmigen
import Signal
, Const
2 from soc
.fu
.alu
.alu_input_record
import CompLDSTOpSubset
3 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
4 from ieee754
.fpcommon
.getop
import FPPipeContext
5 from soc
.decoder
.power_decoder2
import Data
8 class LDSTInputData(IntegerData
):
9 regspec
= [('INT', 'a', '0:63'),
12 ('XER', 'xer_so', '32')]
14 def __init__(self
, pspec
):
15 super().__init
__(pspec
)
16 self
.a
= Signal(64, reset_less
=True) # RA
17 self
.b
= Signal(64, reset_less
=True) # RB/immediate
18 self
.c
= Signal(64, reset_less
=True) # RC
19 self
.xer_so
= Signal(reset_less
=True) # XER bit 32: SO
22 yield from super().__iter
__()
30 return lst
+ [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
), self
.c
.eq(i
.c
),
31 self
.xer_so
.eq(i
.xer_so
)]
34 class LDSTOutputData(IntegerData
):
35 regspec
= [('INT', 'o', '0:63'),
36 ('INT', 'ea', '0:63'),
38 ('XER', 'xer_so', '32')]
39 def __init__(self
, pspec
):
40 super().__init
__(pspec
)
41 self
.o
= Data(64, name
="stage_o")
42 self
.ea
= Data(64, name
="ea")
43 self
.cr0
= Data(4, name
="cr0")
44 self
.xer_so
= Data(1, name
="xer_so")
47 yield from super().__iter
__()
56 return lst
+ [self
.o
.eq(i
.o
),
59 self
.xer_so
.eq(i
.xer_so
)]
62 class LDSTPipeSpec(CommonPipeSpec
):
63 regspec
= (LDSTInputData
.regspec
, LDSTOutputData
.regspec
)
64 opsubsetkls
= CompLDSTOpSubset