src/soc/fu/ldst/pipe_data.py

   1 from nmigen import Signal, Const
   2 from soc.fu.alu.alu_input_record import CompLDSTOpSubset
   3 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
   4 from ieee754.fpcommon.getop import FPPipeContext
   5 from soc.decoder.power_decoder2 import Data
   6
   7
   8 class LDSTInputData(IntegerData):
   9     regspec = [('INT', 'ra', '0:63'),
  10                ('INT', 'rb', '0:63'),
  11                ('INT', 'rc', '0:63'),
  12                ('XER', 'xer_so', '32')]
  13                ]
  14     def __init__(self, pspec):
  15         super().__init__(pspec)
  16         self.ra = Signal(64, reset_less=True) # RA
  17         self.rb = Signal(64, reset_less=True) # RB/immediate
  18         self.rc = Signal(64, reset_less=True) # RC
  19         self.xer_so = Signal(reset_less=True) # XER bit 32: SO
  20         # convenience
  21         self.rs = self.rc
  22
  23     def __iter__(self):
  24         yield from super().__iter__()
  25         yield self.ra
  26         yield self.rb
  27         yield self.rc
  28         yield self.xer_so
  29
  30     def eq(self, i):
  31         lst = super().eq(i)
  32         return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb), self.rc.eq(i.rc),
  33                       self.xer_so.eq(i.xer_so)]
  34
  35
  36 class LDSTOutputData(IntegerData):
  37     regspec = [('INT', 'o', '0:63'),
  38                ('INT', 'o1', '0:63'),
  39                ('CR', 'cr_a', '0:3'),
  40                ('XER', 'xer_so', '32')]
  41     def __init__(self, pspec):
  42         super().__init__(pspec)
  43         self.o = Data(64, name="stage_o")
  44         self.o1 = Data(64, name="o1")
  45         self.cr_a = Data(4, name="cr_a")
  46         self.xer_so = Data(1, name="xer_so")
  47         # convenience
  48         self.cr0, self.ea = self.cr_a, self.o1
  49
  50     def __iter__(self):
  51         yield from super().__iter__()
  52         yield self.o
  53         yield self.o1
  54         yield self.xer_ca
  55         yield self.cr_a
  56         yield self.xer_so
  57
  58     def eq(self, i):
  59         lst = super().eq(i)
  60         return lst + [self.o.eq(i.o),
  61                       self.o1.eq(i.o1),
  62                       self.cr_a.eq(i.cr_a),
  63                       self.xer_so.eq(i.xer_so)]
  64
  65
  66 class LDSTPipeSpec(CommonPipeSpec):
  67     regspec = (LDSTInputData.regspec, LDSTOutputData.regspec)
  68     opsubsetkls = CompLDSTOpSubset