src/soc/fu/ldst/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import TestCase
  16 from soc.fu.ldst.pipe_data import LDSTPipeSpec
  17 import random
  18
  19
  20 def get_cu_inputs(dec2, sim):
  21     """naming (res) must conform to LDSTFunctionUnit input regspec
  22     """
  23     res = {}
  24
  25     # RA
  26     reg1_ok = yield dec2.e.read_reg1.ok
  27     if reg1_ok:
  28         data1 = yield dec2.e.read_reg1.data
  29         res['ra'] = sim.gpr(data1).value
  30
  31     # RB (or immediate)
  32     reg2_ok = yield dec2.e.read_reg2.ok
  33     if reg2_ok:
  34         data2 = yield dec2.e.read_reg2.data
  35         res['rb'] = sim.gpr(data2).value
  36
  37     # RC
  38     reg3_ok = yield dec2.e.read_reg3.ok
  39     if reg3_ok:
  40         data3 = yield dec2.e.read_reg3.data
  41         res['rc'] = sim.gpr(data3).value
  42
  43     # XER.so
  44     oe = yield dec2.e.oe.data[0] & dec2.e.oe.ok
  45     if oe:
  46         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  47         res['xer_so'] = so
  48
  49     return res
  50
  51
  52 class LDSTTestCase(FHDLTestCase):
  53     test_data = []
  54
  55     def __init__(self, name):
  56         super().__init__(name)
  57         self.test_name = name
  58
  59     def run_tst_program(self, prog, initial_regs=None,
  60                         initial_sprs=None, initial_mem=None):
  61         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs,
  62                       mem=initial_mem)
  63         self.test_data.append(tc)
  64
  65     def test_1_load(self):
  66         lst = ["lhz 3, 0(1)"]
  67         initial_regs = [0] * 32
  68         initial_regs[1] = 0x0004
  69         initial_regs[2] = 0x0008
  70         initial_mem = {0x0000: (0x5432123412345678, 8),
  71                        0x0008: (0xabcdef0187654321, 8),
  72                        0x0020: (0x1828384822324252, 8),
  73                         }
  74         self.run_tst_program(Program(lst), initial_regs,
  75                              initial_mem=initial_mem)
  76
  77     def test_2_load_store(self):
  78         lst = [
  79                "stb 3, 1(2)",
  80                "lbz 4, 1(2)",
  81         ]
  82         initial_regs = [0] * 32
  83         initial_regs[1] = 0x0004
  84         initial_regs[2] = 0x0008
  85         initial_regs[3] = 0x00ee
  86         initial_mem = {0x0000: (0x5432123412345678, 8),
  87                        0x0008: (0xabcdef0187654321, 8),
  88                        0x0020: (0x1828384822324252, 8),
  89                         }
  90         self.run_tst_program(Program(lst), initial_regs,
  91                              initial_mem=initial_mem)
  92
  93     def test_3_load_store(self):
  94         lst = ["sth 4, 0(2)",
  95                "lhz 4, 0(2)"]
  96         initial_regs = [0] * 32
  97         initial_regs[1] = 0x1004
  98         initial_regs[2] = 0x1002
  99         initial_regs[3] = 0x15eb
 100         initial_mem = {0x1000: (0x5432123412345678, 8),
 101                        0x1008: (0xabcdef0187654321, 8),
 102                        0x1020: (0x1828384822324252, 8),
 103                         }
 104         self.run_tst_program(Program(lst), initial_regs,
 105                              initial_mem=initial_mem)
 106