src/soc/fu/ldst/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.cli import rtlil
   4 import unittest
   5 from soc.decoder.isa.caller import special_sprs
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
   9 from soc.decoder.selectable_int import SelectableInt
  10 from soc.simulator.program import Program
  11 from soc.decoder.isa.all import ISA
  12 from soc.config.endian import bigendian
  13
  14
  15 from soc.fu.test.common import TestAccumulatorBase, TestCase
  16 from soc.fu.ldst.pipe_data import LDSTPipeSpec
  17 import random
  18
  19
  20 def get_cu_inputs(dec2, sim):
  21     """naming (res) must conform to LDSTFunctionUnit input regspec
  22     """
  23     res = {}
  24
  25     # RA
  26     reg1_ok = yield dec2.e.read_reg1.ok
  27     if reg1_ok:
  28         data1 = yield dec2.e.read_reg1.data
  29         res['ra'] = sim.gpr(data1).value
  30
  31     # RB (or immediate)
  32     reg2_ok = yield dec2.e.read_reg2.ok
  33     if reg2_ok:
  34         data2 = yield dec2.e.read_reg2.data
  35         res['rb'] = sim.gpr(data2).value
  36
  37     # RC
  38     reg3_ok = yield dec2.e.read_reg3.ok
  39     if reg3_ok:
  40         data3 = yield dec2.e.read_reg3.data
  41         res['rc'] = sim.gpr(data3).value
  42
  43     # XER.so
  44     oe = yield dec2.e.do.oe.data[0] & dec2.e.do.oe.ok
  45     if oe:
  46         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  47         res['xer_so'] = so
  48
  49     return res
  50
  51
  52 class LDSTTestCase(TestAccumulatorBase):
  53
  54     def case_1_load(self):
  55         lst = ["lhz 3, 0(1)"]
  56         initial_regs = [0] * 32
  57         initial_regs[1] = 0x0004
  58         initial_regs[2] = 0x0008
  59         initial_mem = {0x0000: (0x5432123412345678, 8),
  60                        0x0008: (0xabcdef0187654321, 8),
  61                        0x0020: (0x1828384822324252, 8),
  62                         }
  63         self.add_case(Program(lst, bigendian), initial_regs,
  64                              initial_mem=initial_mem)
  65
  66     def case_2_load_store(self):
  67         lst = [
  68                "stb 3, 1(2)",
  69                "lbz 4, 1(2)",
  70         ]
  71         initial_regs = [0] * 32
  72         initial_regs[1] = 0x0004
  73         initial_regs[2] = 0x0008
  74         initial_regs[3] = 0x00ee
  75         initial_mem = {0x0000: (0x5432123412345678, 8),
  76                        0x0008: (0xabcdef0187654321, 8),
  77                        0x0020: (0x1828384822324252, 8),
  78                         }
  79         self.add_case(Program(lst, bigendian), initial_regs,
  80                              initial_mem=initial_mem)
  81
  82     def case_3_load_store(self):
  83         lst = ["sth 4, 0(2)",
  84                "lhz 4, 0(2)"]
  85         initial_regs = [0] * 32
  86         initial_regs[1] = 0x0004
  87         initial_regs[2] = 0x0002
  88         initial_regs[3] = 0x15eb
  89         initial_mem = {0x0000: (0x5432123412345678, 8),
  90                        0x0008: (0xabcdef0187654321, 8),
  91                        0x0020: (0x1828384822324252, 8),
  92                         }
  93         self.add_case(Program(lst, bigendian), initial_regs,
  94                              initial_mem=initial_mem)
  95
  96     def case_4_load_store_rev_ext(self):
  97         lst = ["stwx 1, 4, 2",
  98                "lwbrx 3, 4, 2"]
  99         initial_regs = [0] * 32
 100         initial_regs[1] = 0x5678
 101         initial_regs[2] = 0x001c
 102         initial_regs[4] = 0x0008
 103         initial_mem = {0x0000: (0x5432123412345678, 8),
 104                        0x0008: (0xabcdef0187654321, 8),
 105                        0x0020: (0x1828384822324252, 8),
 106                         }
 107         self.add_case(Program(lst, bigendian), initial_regs,
 108                              initial_mem=initial_mem)
 109
 110     def case_5_load_store_rev_ext(self):
 111         lst = ["stwbrx 1, 4, 2",
 112                "lwzx 3, 4, 2"]
 113         initial_regs = [0] * 32
 114         initial_regs[1] = 0x5678
 115         initial_regs[2] = 0x001c
 116         initial_regs[4] = 0x0008
 117         initial_mem = {0x0000: (0x5432123412345678, 8),
 118                        0x0008: (0xabcdef0187654321, 8),
 119                        0x0020: (0x1828384822324252, 8),
 120                         }
 121         self.add_case(Program(lst, bigendian), initial_regs,
 122                              initial_mem=initial_mem)
 123
 124     def case_6_load_store_rev_ext(self):
 125         lst = ["stwbrx 1, 4, 2",
 126                "lwbrx 3, 4, 2"]
 127         initial_regs = [0] * 32
 128         initial_regs[1] = 0x5678
 129         initial_regs[2] = 0x001c
 130         initial_regs[4] = 0x0008
 131         initial_mem = {0x0000: (0x5432123412345678, 8),
 132                        0x0008: (0xabcdef0187654321, 8),
 133                        0x0020: (0x1828384822324252, 8),
 134                         }
 135         self.add_case(Program(lst, bigendian), initial_regs,
 136                              initial_mem=initial_mem)
 137
 138     def case_7_load_store_d(self):
 139         lst = [
 140                "std 3, 0(2)",
 141                "ld 4, 0(2)",
 142         ]
 143         initial_regs = [0] * 32
 144         initial_regs[1] = 0x0004
 145         initial_regs[2] = 0x0008
 146         initial_regs[3] = 0x00ee
 147         initial_mem = {0x0000: (0x5432123412345678, 8),
 148                        0x0008: (0xabcdef0187654321, 8),
 149                        0x0020: (0x1828384822324252, 8),
 150                         }
 151         self.add_case(Program(lst, bigendian), initial_regs,
 152                              initial_mem=initial_mem)
 153
 154     def case_8_load_store_d_update(self):
 155         lst = [
 156                "stdu 3, 0(2)",
 157                "ld 4, 0(2)",
 158         ]
 159         initial_regs = [0] * 32
 160         initial_regs[1] = 0x0004
 161         initial_regs[2] = 0x0008
 162         initial_regs[3] = 0x00ee
 163         initial_mem = {0x0000: (0x5432123412345678, 8),
 164                        0x0008: (0xabcdef0187654321, 8),
 165                        0x0020: (0x1828384822324252, 8),
 166                         }
 167         self.add_case(Program(lst, bigendian), initial_regs,
 168                              initial_mem=initial_mem)
 169