1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.cli
import rtlil
5 from soc
.decoder
.isa
.caller
import special_sprs
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.decoder
.power_enums
import (XER_bits
, Function
, MicrOp
, CryIn
)
9 from soc
.decoder
.selectable_int
import SelectableInt
10 from soc
.simulator
.program
import Program
11 from soc
.decoder
.isa
.all
import ISA
12 from soc
.config
.endian
import bigendian
15 from soc
.fu
.test
.common
import TestAccumulatorBase
, TestCase
16 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
20 def get_cu_inputs(dec2
, sim
):
21 """naming (res) must conform to LDSTFunctionUnit input regspec
26 reg1_ok
= yield dec2
.e
.read_reg1
.ok
28 data1
= yield dec2
.e
.read_reg1
.data
29 res
['ra'] = sim
.gpr(data1
).value
32 reg2_ok
= yield dec2
.e
.read_reg2
.ok
34 data2
= yield dec2
.e
.read_reg2
.data
35 res
['rb'] = sim
.gpr(data2
).value
38 reg3_ok
= yield dec2
.e
.read_reg3
.ok
40 data3
= yield dec2
.e
.read_reg3
.data
41 res
['rc'] = sim
.gpr(data3
).value
44 oe
= yield dec2
.e
.do
.oe
.data
[0] & dec2
.e
.do
.oe
.ok
46 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
52 class LDSTTestCase(TestAccumulatorBase
):
54 def case_1_load(self
):
56 initial_regs
= [0] * 32
57 initial_regs
[1] = 0x0004
58 initial_regs
[2] = 0x0008
59 initial_mem
= {0x0000: (0x5432123412345678, 8),
60 0x0008: (0xabcdef0187654321, 8),
61 0x0020: (0x1828384822324252, 8),
63 self
.add_case(Program(lst
, bigendian
), initial_regs
,
64 initial_mem
=initial_mem
)
66 def case_2_load_store(self
):
71 initial_regs
= [0] * 32
72 initial_regs
[1] = 0x0004
73 initial_regs
[2] = 0x0008
74 initial_regs
[3] = 0x00ee
75 initial_mem
= {0x0000: (0x5432123412345678, 8),
76 0x0008: (0xabcdef0187654321, 8),
77 0x0020: (0x1828384822324252, 8),
79 self
.add_case(Program(lst
, bigendian
), initial_regs
,
80 initial_mem
=initial_mem
)
82 def case_3_load_store(self
):
85 initial_regs
= [0] * 32
86 initial_regs
[1] = 0x0004
87 initial_regs
[2] = 0x0002
88 initial_regs
[3] = 0x15eb
89 initial_mem
= {0x0000: (0x5432123412345678, 8),
90 0x0008: (0xabcdef0187654321, 8),
91 0x0020: (0x1828384822324252, 8),
93 self
.add_case(Program(lst
, bigendian
), initial_regs
,
94 initial_mem
=initial_mem
)
96 def case_4_load_store_rev_ext(self
):
97 lst
= ["stwx 1, 4, 2",
99 initial_regs
= [0] * 32
100 initial_regs
[1] = 0x5678
101 initial_regs
[2] = 0x001c
102 initial_regs
[4] = 0x0008
103 initial_mem
= {0x0000: (0x5432123412345678, 8),
104 0x0008: (0xabcdef0187654321, 8),
105 0x0020: (0x1828384822324252, 8),
107 self
.add_case(Program(lst
, bigendian
), initial_regs
,
108 initial_mem
=initial_mem
)
110 def case_5_load_store_rev_ext(self
):
111 lst
= ["stwbrx 1, 4, 2",
113 initial_regs
= [0] * 32
114 initial_regs
[1] = 0x5678
115 initial_regs
[2] = 0x001c
116 initial_regs
[4] = 0x0008
117 initial_mem
= {0x0000: (0x5432123412345678, 8),
118 0x0008: (0xabcdef0187654321, 8),
119 0x0020: (0x1828384822324252, 8),
121 self
.add_case(Program(lst
, bigendian
), initial_regs
,
122 initial_mem
=initial_mem
)
124 def case_6_load_store_rev_ext(self
):
125 lst
= ["stwbrx 1, 4, 2",
127 initial_regs
= [0] * 32
128 initial_regs
[1] = 0x5678
129 initial_regs
[2] = 0x001c
130 initial_regs
[4] = 0x0008
131 initial_mem
= {0x0000: (0x5432123412345678, 8),
132 0x0008: (0xabcdef0187654321, 8),
133 0x0020: (0x1828384822324252, 8),
135 self
.add_case(Program(lst
, bigendian
), initial_regs
,
136 initial_mem
=initial_mem
)
138 def case_7_load_store_d(self
):
143 initial_regs
= [0] * 32
144 initial_regs
[1] = 0x0004
145 initial_regs
[2] = 0x0008
146 initial_regs
[3] = 0x00ee
147 initial_mem
= {0x0000: (0x5432123412345678, 8),
148 0x0008: (0xabcdef0187654321, 8),
149 0x0020: (0x1828384822324252, 8),
151 self
.add_case(Program(lst
, bigendian
), initial_regs
,
152 initial_mem
=initial_mem
)
154 def case_8_load_store_d_update(self
):
159 initial_regs
= [0] * 32
160 initial_regs
[1] = 0x0004
161 initial_regs
[2] = 0x0008
162 initial_regs
[3] = 0x00ee
163 initial_mem
= {0x0000: (0x5432123412345678, 8),
164 0x0008: (0xabcdef0187654321, 8),
165 0x0020: (0x1828384822324252, 8),
167 self
.add_case(Program(lst
, bigendian
), initial_regs
,
168 initial_mem
=initial_mem
)
170 def case_9_load_algebraic_1(self
):
171 lst
= ["lwax 3, 4, 2"]
172 initial_regs
= [0] * 32
173 initial_regs
[1] = 0x5678
174 initial_regs
[2] = 0x001c
175 initial_regs
[4] = 0x0008
176 initial_mem
= {0x0000: (0x5432123412345678, 8),
177 0x0008: (0xabcdef0187654321, 8),
178 0x0020: (0xf000000f0000ffff, 8),
180 self
.add_case(Program(lst
, bigendian
), initial_regs
,
181 initial_mem
=initial_mem
)
183 def case_9_load_algebraic_2(self
):
184 lst
= ["lwax 3, 4, 2"]
185 initial_regs
= [0] * 32
186 initial_regs
[1] = 0x5678
187 initial_regs
[2] = 0x001c
188 initial_regs
[4] = 0x0008
189 initial_mem
= {0x0000: (0x5432123412345678, 8),
190 0x0008: (0xabcdef0187654321, 8),
191 0x0020: (0x7000000f0000ffff, 8),
193 self
.add_case(Program(lst
, bigendian
), initial_regs
,
194 initial_mem
=initial_mem
)
196 def case_9_load_algebraic_3(self
):
197 lst
= ["lwaux 3, 4, 2"]
198 initial_regs
= [0] * 32
199 initial_regs
[1] = 0x5678
200 initial_regs
[2] = 0x001c
201 initial_regs
[4] = 0x0008
202 initial_mem
= {0x0000: (0x5432123412345678, 8),
203 0x0008: (0xabcdef0187654321, 8),
204 0x0020: (0xf000000f0000ffff, 8),
206 self
.add_case(Program(lst
, bigendian
), initial_regs
,
207 initial_mem
=initial_mem
)
209 def case_9_load_algebraic_4(self
):
210 lst
= ["lwa 3, 4(4)"]
211 initial_regs
= [0] * 32
212 initial_regs
[1] = 0x5678
213 initial_regs
[4] = 0x0020
214 initial_mem
= {0x0000: (0x5432123412345678, 8),
215 0x0008: (0xabcdef0187654321, 8),
216 0x0020: (0xf000000f1234ffff, 8),
218 self
.add_case(Program(lst
, bigendian
), initial_regs
,
219 initial_mem
=initial_mem
)