1 # This stage is intended to adjust the input data before sending it to
2 # the actual Logical pipeline. Things like handling inverting the input, xer_ca
3 # generation for subtraction, and handling of immediates should happen
5 from soc
.fu
.common_input_stage
import CommonInputStage
6 from soc
.fu
.logical
.pipe_data
import LogicalInputData
9 class LogicalInputStage(CommonInputStage
):
10 def __init__(self
, pspec
):
11 super().__init
__(pspec
, "input")
12 self
.invert_op
= "rb" # inversion is on register b
15 return LogicalInputData(self
.pspec
)
18 return LogicalInputData(self
.pspec
)
20 def elaborate(self
, platform
):
21 m
= super().elaborate(platform
) # covers B-invert, carry, excludes SO