src/soc/fu/logical/output_stage.py

   1 # This stage is intended to handle the gating of carry and overflow
   2 # out, summary overflow generation, and updating the condition
   3 # register
   4 from nmigen import (Module, Signal, Cat, Repl)
   5 from nmutil.pipemodbase import PipeModBase
   6 from soc.fu.common_output_stage import CommonOutputStage
   7 from soc.fu.logical.pipe_data import (LogicalInputData, LogicalOutputData,
   8                                       LogicalOutputDataFinal)
   9 from ieee754.part.partsig import SimdSignal
  10 from openpower.decoder.power_enums import MicrOp
  11
  12
  13 class LogicalOutputStage(CommonOutputStage):
  14
  15     def ispec(self):
  16         return LogicalOutputData(self.pspec)
  17
  18     def ospec(self):
  19         return LogicalOutputDataFinal(self.pspec)
  20