src/soc/fu/logical/output_stage.py

   1 # This stage is intended to handle the gating of carry and overflow
   2 # out, summary overflow generation, and updating the condition
   3 # register
   4 from nmigen import (Module, Signal, Cat, Repl)
   5 from nmutil.pipemodbase import PipeModBase
   6 from soc.fu.common_output_stage import CommonOutputStage
   7 from soc.fu.logical.pipe_data import LogicalInputData, LogicalOutputData
   8 from ieee754.part.partsig import PartitionedSignal
   9 from soc.decoder.power_enums import MicrOp
  10
  11
  12 class LogicalOutputStage(CommonOutputStage):
  13
  14     def ispec(self):
  15         return LogicalOutputData(self.pspec)
  16
  17     def ospec(self):
  18         return LogicalOutputData(self.pspec)
  19