src/soc/fu/logical/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.pipe_data import IntegerData
   4 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
   5 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
   6
   7
   8 class LogicalInputData(IntegerData):
   9     regspec = [('INT', 'a', '0:63'),
  10                ('INT', 'rb', '0:63'),
  11                ('XER', 'xer_so', '32'),
  12                ('XER', 'xer_ca', '34,45')]
  13     def __init__(self, pspec):
  14         super().__init__(pspec)
  15         self.a = Signal(64, reset_less=True) # RA
  16         self.b = Signal(64, reset_less=True) # RB/immediate
  17         self.xer_so = Signal(reset_less=True)    # XER bit 32: SO
  18         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  19
  20     def __iter__(self):
  21         yield from super().__iter__()
  22         yield self.a
  23         yield self.b
  24         yield self.xer_ca
  25         yield self.xer_so
  26
  27     def eq(self, i):
  28         lst = super().eq(i)
  29         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  30                       self.xer_ca.eq(i.xer_ca),
  31                       self.xer_so.eq(i.xer_so)]
  32
  33
  34 # TODO: replace CompALUOpSubset with CompLogicalOpSubset
  35 class LogicalPipeSpec(CommonPipeSpec):
  36     regspec = (LogicalInputData.regspec, ALUOutputData.regspec)
  37     opsubsetkls = CompALUOpSubset