37e86d5aec1834aaf7ce5c78708b10619f424e8f
1 from nmigen
import Signal
, Const
, Cat
2 from ieee754
.fpcommon
.getop
import FPPipeContext
3 from soc
.fu
.pipe_data
import IntegerData
4 from soc
.decoder
.power_decoder2
import Data
5 from soc
.fu
.alu
.pipe_data
import ALUOutputData
, CommonPipeSpec
6 from soc
.fu
.logical
.logical_input_record
import CompLogicalOpSubset
9 class LogicalInputData(IntegerData
):
10 regspec
= [('INT', 'ra', '0:63'),
11 ('INT', 'rb', '0:63'),
13 def __init__(self
, pspec
):
14 super().__init
__(pspec
)
15 self
.ra
= Signal(64, reset_less
=True) # RA
16 self
.rb
= Signal(64, reset_less
=True) # RB/immediate
18 self
.a
, self
.b
= self
.ra
, self
.rb
21 yield from super().__iter
__()
27 return lst
+ [self
.ra
.eq(i
.ra
), self
.rb
.eq(i
.rb
),
31 class LogicalOutputData(IntegerData
):
32 regspec
= [('INT', 'o', '0:63'),
33 ('CR', 'cr_a', '0:3'),
34 ('XER', 'xer_ca', '34,45'),
36 def __init__(self
, pspec
):
37 super().__init
__(pspec
)
38 self
.o
= Data(64, name
="stage_o") # RT
39 self
.cr_a
= Data(4, name
="cr_a")
40 self
.xer_ca
= Data(2, name
="xer_co") # bit0: ca, bit1: ca32
45 yield from super().__iter
__()
52 return lst
+ [self
.o
.eq(i
.o
),
53 self
.xer_ca
.eq(i
.xer_ca
),
58 class LogicalPipeSpec(CommonPipeSpec
):
59 regspec
= (LogicalInputData
.regspec
, LogicalOutputData
.regspec
)
60 opsubsetkls
= CompLogicalOpSubset