src/soc/fu/logical/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.pipe_data import IntegerData
   4 from soc.decoder.power_decoder2 import Data
   5 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
   6 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
   7
   8
   9 class LogicalInputData(IntegerData):
  10     regspec = [('INT', 'a', '0:63'),
  11                ('INT', 'rb', '0:63'),
  12                ('XER', 'xer_ca', '34,45')]
  13     def __init__(self, pspec):
  14         super().__init__(pspec)
  15         self.a = Signal(64, reset_less=True) # RA
  16         self.b = Signal(64, reset_less=True) # RB/immediate
  17         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  18
  19     def __iter__(self):
  20         yield from super().__iter__()
  21         yield self.a
  22         yield self.b
  23         yield self.xer_ca
  24
  25     def eq(self, i):
  26         lst = super().eq(i)
  27         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  28                       self.xer_ca.eq(i.xer_ca) ]
  29
  30
  31 class LogicalOutputData(IntegerData):
  32     regspec = [('INT', 'o', '0:63'),
  33                ('CR', 'cr0', '0:3'),
  34                ('XER', 'xer_ca', '34,45'),
  35                ('XER', 'xer_so', '32')]
  36     def __init__(self, pspec):
  37         super().__init__(pspec)
  38         self.o = Signal(64, reset_less=True, name="stage_o")
  39         self.cr0 = Data(4, name="cr0")
  40         self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
  41         self.xer_so = Data(1, name="xer_so")
  42
  43     def __iter__(self):
  44         yield from super().__iter__()
  45         yield self.o
  46         yield self.xer_ca
  47         yield self.cr0
  48         yield self.xer_so
  49
  50     def eq(self, i):
  51         lst = super().eq(i)
  52         return lst + [self.o.eq(i.o),
  53                       self.xer_ca.eq(i.xer_ca),
  54                       self.cr0.eq(i.cr0),
  55                       self.xer_so.eq(i.xer_so)]
  56
  57
  58 class LogicalPipeSpec(CommonPipeSpec):
  59     regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
  60     opsubsetkls = CompLogicalOpSubset