src/soc/fu/logical/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.alu.pipe_data import IntegerData
   4
   5
   6 class LogicalInputData(IntegerData):
   7     regspec = [('INT', 'a', '0:63'),
   8                ('INT', 'rb', '0:63'),
   9                ('XER', 'xer_so', '32'),
  10                ('XER', 'xer_ca', '34,45')]
  11     def __init__(self, pspec):
  12         super().__init__(pspec)
  13         self.a = Signal(64, reset_less=True) # RA
  14         self.b = Signal(64, reset_less=True) # RB/immediate
  15         self.xer_so = Signal(reset_less=True)    # XER bit 32: SO
  16         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  17
  18     def __iter__(self):
  19         yield from super().__iter__()
  20         yield self.a
  21         yield self.b
  22         yield self.xer_ca
  23         yield self.xer_so
  24
  25     def eq(self, i):
  26         lst = super().eq(i)
  27         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  28                       self.xer_ca.eq(i.xer_ca),
  29                       self.xer_so.eq(i.xer_so)]