aed7868977d08e06aaaadf9cca38b19036153d1d
1 from nmigen
import Signal
, Const
2 from ieee754
.fpcommon
.getop
import FPPipeContext
3 from soc
.fu
.alu
.pipe_data
import IntegerData
6 class LogicalInputData(IntegerData
):
7 def __init__(self
, pspec
):
8 super().__init
__(pspec
)
9 self
.a
= Signal(64, reset_less
=True) # RA
10 self
.b
= Signal(64, reset_less
=True) # RB/immediate
11 self
.xer_so
= Signal(reset_less
=True) # XER bit 32: SO
12 self
.xer_ca
= Signal(2, reset_less
=True) # XER bit 34/45: CA/CA32
15 yield from super().__iter
__()
23 return lst
+ [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
),
24 self
.xer_ca
.eq(i
.xer_ca
),
25 self
.xer_so
.eq(i
.xer_so
)]