ba24ce6d4bbf706d49c1a1c6f26d4b000053e770
1 from nmigen
import Signal
, Const
, Cat
2 from ieee754
.fpcommon
.getop
import FPPipeContext
3 from soc
.fu
.pipe_data
import IntegerData
4 from soc
.decoder
.power_decoder2
import Data
5 from soc
.fu
.alu
.pipe_data
import ALUOutputData
, CommonPipeSpec
6 from soc
.fu
.logical
.logical_input_record
import CompLogicalOpSubset
9 class LogicalInputData(IntegerData
):
10 regspec
= [('INT', 'a', '0:63'),
13 def __init__(self
, pspec
):
14 super().__init
__(pspec
)
15 self
.a
= Signal(64, reset_less
=True) # RA
16 self
.b
= Signal(64, reset_less
=True) # RB/immediate
19 yield from super().__iter
__()
25 return lst
+ [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
),
29 class LogicalOutputData(IntegerData
):
30 regspec
= [('INT', 'o', '0:63'),
32 ('XER', 'xer_ca', '34,45'),
34 def __init__(self
, pspec
):
35 super().__init
__(pspec
)
36 self
.o
= Data(64, name
="stage_o") # RT
37 self
.cr0
= Data(4, name
="cr0")
38 self
.xer_ca
= Data(2, name
="xer_co") # bit0: ca, bit1: ca32
41 yield from super().__iter
__()
48 return lst
+ [self
.o
.eq(i
.o
),
49 self
.xer_ca
.eq(i
.xer_ca
),
54 class LogicalPipeSpec(CommonPipeSpec
):
55 regspec
= (LogicalInputData
.regspec
, LogicalOutputData
.regspec
)
56 opsubsetkls
= CompLogicalOpSubset
57 def rdflags(self
, e
): # in order of regspec
58 reg1_ok
= e
.read_reg1
.ok
# RA
59 reg2_ok
= e
.read_reg2
.ok
# RB
60 return Cat(reg1_ok
, reg2_ok
) # RA RB