src/soc/fu/logical/pipe_data.py

   1 from nmigen import Signal, Const, Cat
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.pipe_data import IntegerData
   4 from soc.decoder.power_decoder2 import Data
   5 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
   6 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
   7
   8
   9 class LogicalInputData(IntegerData):
  10     regspec = [('INT', 'a', '0:63'),
  11                ('INT', 'b', '0:63'),
  12                ]
  13     def __init__(self, pspec):
  14         super().__init__(pspec)
  15         self.a = Signal(64, reset_less=True) # RA
  16         self.b = Signal(64, reset_less=True) # RB/immediate
  17
  18     def __iter__(self):
  19         yield from super().__iter__()
  20         yield self.a
  21         yield self.b
  22
  23     def eq(self, i):
  24         lst = super().eq(i)
  25         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  26                        ]
  27
  28
  29 class LogicalOutputData(IntegerData):
  30     regspec = [('INT', 'o', '0:63'),
  31                ('CR', 'cr0', '0:3'),
  32                ('XER', 'xer_ca', '34,45'),
  33                ]
  34     def __init__(self, pspec):
  35         super().__init__(pspec)
  36         self.o = Data(64, name="stage_o")  # RT
  37         self.cr0 = Data(4, name="cr0")
  38         self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
  39
  40     def __iter__(self):
  41         yield from super().__iter__()
  42         yield self.o
  43         yield self.xer_ca
  44         yield self.cr0
  45
  46     def eq(self, i):
  47         lst = super().eq(i)
  48         return lst + [self.o.eq(i.o),
  49                       self.xer_ca.eq(i.xer_ca),
  50                       self.cr0.eq(i.cr0),
  51                       ]
  52
  53
  54 class LogicalPipeSpec(CommonPipeSpec):
  55     regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
  56     opsubsetkls = CompLogicalOpSubset
  57     def rdflags(self, e): # in order of regspec
  58         reg1_ok = e.read_reg1.ok # RA
  59         reg2_ok = e.read_reg2.ok # RB
  60         return Cat(reg1_ok, reg2_ok) # RA RB