src/soc/fu/logical/test/test_countzero.py

   1 # https://github.com/antonblanchard/microwatt/blob/master/countzero_tb.vhdl
   2 from nmigen import Module, Signal
   3 from nmigen.cli import rtlil
   4 from nmigen.back.pysim import Simulator, Delay
   5 from nmigen.test.utils import FHDLTestCase
   6 import unittest
   7 from soc.fu.logical.countzero import ZeroCounter
   8
   9
  10 class ZeroCounterTestCase(FHDLTestCase):
  11     def test_zerocounter(self):
  12         m = Module()
  13         comb = m.d.comb
  14         m.submodules.dut = dut = ZeroCounter()
  15
  16         sim = Simulator(m)
  17         # sim.add_clock(1e-6)
  18
  19         def process():
  20             print("test zero input")
  21             yield dut.rs_i.eq(0)
  22             yield dut.is_32bit_i.eq(0)
  23             yield dut.count_right_i.eq(0)
  24             yield Delay(1e-6)
  25             result = yield dut.result_o
  26             assert result == 0x40
  27             # report "bad cntlzd 0 = " & to_hstring(result);
  28             assert(result == 0x40)
  29             yield dut.count_right_i.eq(1)
  30             yield Delay(1e-6)
  31             result = yield dut.result_o
  32             # report "bad cntlzd 0 = " & to_hstring(result);
  33             assert(result == 0x40)
  34             yield dut.is_32bit_i.eq(1)
  35             yield dut.count_right_i.eq(0)
  36             yield Delay(1e-6)
  37             result = yield dut.result_o
  38             # report "bad cntlzw 0 = " & to_hstring(result);
  39             assert(result == 0x20)
  40             yield dut.count_right_i.eq(1)
  41             yield Delay(1e-6)
  42             result = yield dut.result_o
  43             # report "bad cntlzw 0 = " & to_hstring(result);
  44             assert(result == 0x20)
  45             # TODO next tests
  46
  47             yield dut.rs_i.eq(0b00010000)
  48             yield dut.is_32bit_i.eq(0)
  49             yield dut.count_right_i.eq(0)
  50             yield Delay(1e-6)
  51             result = yield dut.result_o
  52             assert result == 4, "result %d" % result
  53
  54             yield dut.count_right_i.eq(1)
  55             yield Delay(1e-6)
  56             result = yield dut.result_o
  57             assert result == 59, "result %d" % result
  58
  59             yield dut.is_32bit_i.eq(1)
  60             yield Delay(1e-6)
  61             result = yield dut.result_o
  62             assert result == 27, "result %d" % result
  63
  64             yield dut.rs_i.eq(0b1100000100000000)
  65             yield dut.is_32bit_i.eq(0)
  66             yield dut.count_right_i.eq(0)
  67             yield Delay(1e-6)
  68             result = yield dut.result_o
  69             assert result == 14, "result %d" % result
  70
  71             yield dut.count_right_i.eq(1)
  72             yield Delay(1e-6)
  73             result = yield dut.result_o
  74             assert result == 55, "result %d" % result
  75
  76             yield dut.is_32bit_i.eq(1)
  77             yield Delay(1e-6)
  78             result = yield dut.result_o
  79             assert result == 23, "result %d" % result
  80
  81             yield dut.count_right_i.eq(0)
  82             yield Delay(1e-6)
  83             result = yield dut.result_o
  84             assert result == 14, "result %d" % result
  85
  86
  87         sim.add_process(process)  # or sim.add_sync_process(process), see below
  88
  89         # run test and write vcd
  90         fn = "genullnau"
  91         with sim.write_vcd(fn+".vcd", fn+".gtkw", traces=dut.ports()):
  92             sim.run()
  93
  94     # cntlzd_w
  95     # cnttzd_w
  96
  97
  98 if __name__ == "__main__":
  99
 100     dut = ZeroCounter()
 101     vl = rtlil.convert(dut, ports=dut.ports())
 102     with open("countzero.il", "w") as f:
 103         f.write(vl)
 104
 105     unittest.main()