src/soc/fu/logical/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14 from soc.fu.logical.pipeline import LogicalBasePipe
  15 from soc.fu.logical.pipe_data import LogicalPipeSpec
  16 import random
  17
  18
  19 class TestCase:
  20     def __init__(self, program, regs, sprs, name):
  21         self.program = program
  22         self.regs = regs
  23         self.sprs = sprs
  24         self.name = name
  25
  26
  27 def set_alu_inputs(alu, dec2, sim):
  28     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  29     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  30     # and place it into data_i.b
  31
  32     reg3_ok = yield dec2.e.read_reg3.ok
  33     reg1_ok = yield dec2.e.read_reg1.ok
  34     assert reg3_ok != reg1_ok
  35     if reg3_ok:
  36         data1 = yield dec2.e.read_reg3.data
  37         data1 = sim.gpr(data1).value
  38     elif reg1_ok:
  39         data1 = yield dec2.e.read_reg1.data
  40         data1 = sim.gpr(data1).value
  41     else:
  42         data1 = 0
  43
  44     yield alu.p.data_i.a.eq(data1)
  45
  46     # If there's an immediate, set the B operand to that
  47     reg2_ok = yield dec2.e.read_reg2.ok
  48     imm_ok = yield dec2.e.imm_data.imm_ok
  49     if imm_ok:
  50         data2 = yield dec2.e.imm_data.imm
  51     elif reg2_ok:
  52         data2 = yield dec2.e.read_reg2.data
  53         data2 = sim.gpr(data2).value
  54     else:
  55         data2 = 0
  56     yield alu.p.data_i.b.eq(data2)
  57
  58
  59 def set_extra_alu_inputs(alu, dec2, sim):
  60     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  61     carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  62     yield alu.p.data_i.xer_ca[0].eq(carry)
  63     yield alu.p.data_i.xer_ca[1].eq(carry32)
  64     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  65     yield alu.p.data_i.xer_so.eq(so)
  66
  67
  68 # This test bench is a bit different than is usual. Initially when I
  69 # was writing it, I had all of the tests call a function to create a
  70 # device under test and simulator, initialize the dut, run the
  71 # simulation for ~2 cycles, and assert that the dut output what it
  72 # should have. However, this was really slow, since it needed to
  73 # create and tear down the dut and simulator for every test case.
  74
  75 # Now, instead of doing that, every test case in ALUTestCase puts some
  76 # data into the test_data list below, describing the instructions to
  77 # be tested and the initial state. Once all the tests have been run,
  78 # test_data gets passed to TestRunner which then sets up the DUT and
  79 # simulator once, runs all the data through it, and asserts that the
  80 # results match the pseudocode sim at every cycle.
  81
  82 # By doing this, I've reduced the time it takes to run the test suite
  83 # massively. Before, it took around 1 minute on my computer, now it
  84 # takes around 3 seconds
  85
  86 test_data = []
  87
  88
  89 class LogicalTestCase(FHDLTestCase):
  90     def __init__(self, name):
  91         super().__init__(name)
  92         self.test_name = name
  93
  94     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
  95         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
  96         test_data.append(tc)
  97
  98     def test_rand(self):
  99         insns = ["and", "or", "xor"]
 100         for i in range(40):
 101             choice = random.choice(insns)
 102             lst = [f"{choice} 3, 1, 2"]
 103             initial_regs = [0] * 32
 104             initial_regs[1] = random.randint(0, (1 << 64)-1)
 105             initial_regs[2] = random.randint(0, (1 << 64)-1)
 106             self.run_tst_program(Program(lst), initial_regs)
 107
 108     def test_rand_imm_logical(self):
 109         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
 110         for i in range(10):
 111             choice = random.choice(insns)
 112             imm = random.randint(0, (1 << 16)-1)
 113             lst = [f"{choice} 3, 1, {imm}"]
 114             print(lst)
 115             initial_regs = [0] * 32
 116             initial_regs[1] = random.randint(0, (1 << 64)-1)
 117             self.run_tst_program(Program(lst), initial_regs)
 118
 119     def test_cntz(self):
 120         insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
 121         for i in range(100):
 122             choice = random.choice(insns)
 123             lst = [f"{choice} 3, 1"]
 124             print(lst)
 125             initial_regs = [0] * 32
 126             initial_regs[1] = random.randint(0, (1 << 64)-1)
 127             self.run_tst_program(Program(lst), initial_regs)
 128
 129     def test_parity(self):
 130         insns = ["prtyw", "prtyd"]
 131         for i in range(10):
 132             choice = random.choice(insns)
 133             lst = [f"{choice} 3, 1"]
 134             print(lst)
 135             initial_regs = [0] * 32
 136             initial_regs[1] = random.randint(0, (1 << 64)-1)
 137             self.run_tst_program(Program(lst), initial_regs)
 138
 139     def test_popcnt(self):
 140         insns = ["popcntb", "popcntw", "popcntd"]
 141         for i in range(10):
 142             choice = random.choice(insns)
 143             lst = [f"{choice} 3, 1"]
 144             print(lst)
 145             initial_regs = [0] * 32
 146             initial_regs[1] = random.randint(0, (1 << 64)-1)
 147             self.run_tst_program(Program(lst), initial_regs)
 148
 149     def test_popcnt_edge(self):
 150         insns = ["popcntb", "popcntw", "popcntd"]
 151         for choice in insns:
 152             lst = [f"{choice} 3, 1"]
 153             initial_regs = [0] * 32
 154             initial_regs[1] = -1
 155             self.run_tst_program(Program(lst), initial_regs)
 156
 157     def test_cmpb(self):
 158         lst = ["cmpb 3, 1, 2"]
 159         initial_regs = [0] * 32
 160         initial_regs[1] = 0xdeadbeefcafec0de
 161         initial_regs[2] = 0xd0adb0000afec1de
 162         self.run_tst_program(Program(lst), initial_regs)
 163
 164     def test_bpermd(self):
 165         lst = ["bpermd 3, 1, 2"]
 166         for i in range(20):
 167             initial_regs = [0] * 32
 168             initial_regs[1] = 1<<random.randint(0,63)
 169             initial_regs[2] = 0xdeadbeefcafec0de
 170             self.run_tst_program(Program(lst), initial_regs)
 171
 172     def test_ilang(self):
 173         pspec = LogicalPipeSpec(id_wid=2)
 174         alu = LogicalBasePipe(pspec)
 175         vl = rtlil.convert(alu, ports=alu.ports())
 176         with open("logical_pipeline.il", "w") as f:
 177             f.write(vl)
 178
 179
 180 class TestRunner(FHDLTestCase):
 181     def __init__(self, test_data):
 182         super().__init__("run_all")
 183         self.test_data = test_data
 184
 185     def run_all(self):
 186         m = Module()
 187         comb = m.d.comb
 188         instruction = Signal(32)
 189
 190         pdecode = create_pdecode()
 191
 192         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 193
 194         pspec = LogicalPipeSpec(id_wid=2)
 195         m.submodules.alu = alu = LogicalBasePipe(pspec)
 196
 197         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 198         comb += alu.p.valid_i.eq(1)
 199         comb += alu.n.ready_i.eq(1)
 200         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 201         sim = Simulator(m)
 202
 203         sim.add_clock(1e-6)
 204
 205         def process():
 206             for test in self.test_data:
 207                 print(test.name)
 208                 program = test.program
 209                 self.subTest(test.name)
 210                 simulator = ISA(pdecode2, test.regs, test.sprs, 0)
 211                 gen = program.generate_instructions()
 212                 instructions = list(zip(gen, program.assembly.splitlines()))
 213
 214                 index = simulator.pc.CIA.value//4
 215                 while index < len(instructions):
 216                     ins, code = instructions[index]
 217
 218                     print("0x{:X}".format(ins & 0xffffffff))
 219                     print(code)
 220
 221                     # ask the decoder to decode this binary data (endian'd)
 222                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 223                     yield instruction.eq(ins)          # raw binary instr.
 224                     yield Settle()
 225                     fn_unit = yield pdecode2.e.fn_unit
 226                     self.assertEqual(fn_unit, Function.LOGICAL.value, code)
 227                     yield from set_alu_inputs(alu, pdecode2, simulator)
 228                     yield from set_extra_alu_inputs(alu, pdecode2, simulator)
 229                     yield
 230                     opname = code.split(' ')[0]
 231                     yield from simulator.call(opname)
 232                     index = simulator.pc.CIA.value//4
 233
 234                     vld = yield alu.n.valid_o
 235                     while not vld:
 236                         yield
 237                         vld = yield alu.n.valid_o
 238                     yield
 239                     alu_out = yield alu.n.data_o.o
 240                     out_reg_valid = yield pdecode2.e.write_reg.ok
 241                     if out_reg_valid:
 242                         write_reg_idx = yield pdecode2.e.write_reg.data
 243                         expected = simulator.gpr(write_reg_idx).value
 244                         print(f"expected {expected:x}, actual: {alu_out:x}")
 245                         self.assertEqual(expected, alu_out, code)
 246                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 247                                                             simulator, code)
 248
 249         sim.add_sync_process(process)
 250         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 251                            traces=[]):
 252             sim.run()
 253
 254     def check_extra_alu_outputs(self, alu, dec2, sim, code):
 255         rc = yield dec2.e.rc.data
 256         if rc:
 257             cr_expected = sim.crl[0].get_range().value
 258             cr_actual = yield alu.n.data_o.cr0.data
 259             self.assertEqual(cr_expected, cr_actual, code)
 260
 261
 262 if __name__ == "__main__":
 263     unittest.main(exit=False)
 264     suite = unittest.TestSuite()
 265     suite.addTest(TestRunner(test_data))
 266
 267     runner = unittest.TextTestRunner()
 268     runner.run(suite)