src/soc/fu/logical/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14 from soc.fu.test.common import TestCase, ALUHelpers
  15 from soc.fu.logical.pipeline import LogicalBasePipe
  16 from soc.fu.logical.pipe_data import LogicalPipeSpec
  17 import random
  18
  19
  20 def get_cu_inputs(dec2, sim):
  21     """naming (res) must conform to LogicalFunctionUnit input regspec
  22     """
  23     res = {}
  24
  25     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  26     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  27
  28     return res
  29
  30
  31 def set_alu_inputs(alu, dec2, sim):
  32     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  33     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  34     # and place it into data_i.b
  35
  36     inp = yield from get_cu_inputs(dec2, sim)
  37     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  38     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  39
  40
  41 # This test bench is a bit different than is usual. Initially when I
  42 # was writing it, I had all of the tests call a function to create a
  43 # device under test and simulator, initialize the dut, run the
  44 # simulation for ~2 cycles, and assert that the dut output what it
  45 # should have. However, this was really slow, since it needed to
  46 # create and tear down the dut and simulator for every test case.
  47
  48 # Now, instead of doing that, every test case in ALUTestCase puts some
  49 # data into the test_data list below, describing the instructions to
  50 # be tested and the initial state. Once all the tests have been run,
  51 # test_data gets passed to TestRunner which then sets up the DUT and
  52 # simulator once, runs all the data through it, and asserts that the
  53 # results match the pseudocode sim at every cycle.
  54
  55 # By doing this, I've reduced the time it takes to run the test suite
  56 # massively. Before, it took around 1 minute on my computer, now it
  57 # takes around 3 seconds
  58
  59
  60 class LogicalTestCase(FHDLTestCase):
  61     test_data = []
  62     def __init__(self, name):
  63         super().__init__(name)
  64         self.test_name = name
  65
  66     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  67         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  68         self.test_data.append(tc)
  69
  70     def test_rand(self):
  71         insns = ["and", "or", "xor"]
  72         for i in range(40):
  73             choice = random.choice(insns)
  74             lst = [f"{choice} 3, 1, 2"]
  75             initial_regs = [0] * 32
  76             initial_regs[1] = random.randint(0, (1 << 64)-1)
  77             initial_regs[2] = random.randint(0, (1 << 64)-1)
  78             self.run_tst_program(Program(lst), initial_regs)
  79
  80     def test_rand_imm_logical(self):
  81         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
  82         for i in range(10):
  83             choice = random.choice(insns)
  84             imm = random.randint(0, (1 << 16)-1)
  85             lst = [f"{choice} 3, 1, {imm}"]
  86             print(lst)
  87             initial_regs = [0] * 32
  88             initial_regs[1] = random.randint(0, (1 << 64)-1)
  89             self.run_tst_program(Program(lst), initial_regs)
  90
  91     def test_cntz(self):
  92         insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
  93         for i in range(100):
  94             choice = random.choice(insns)
  95             lst = [f"{choice} 3, 1"]
  96             print(lst)
  97             initial_regs = [0] * 32
  98             initial_regs[1] = random.randint(0, (1 << 64)-1)
  99             self.run_tst_program(Program(lst), initial_regs)
 100
 101     def test_parity(self):
 102         insns = ["prtyw", "prtyd"]
 103         for i in range(10):
 104             choice = random.choice(insns)
 105             lst = [f"{choice} 3, 1"]
 106             print(lst)
 107             initial_regs = [0] * 32
 108             initial_regs[1] = random.randint(0, (1 << 64)-1)
 109             self.run_tst_program(Program(lst), initial_regs)
 110
 111     def test_popcnt(self):
 112         insns = ["popcntb", "popcntw", "popcntd"]
 113         for i in range(10):
 114             choice = random.choice(insns)
 115             lst = [f"{choice} 3, 1"]
 116             print(lst)
 117             initial_regs = [0] * 32
 118             initial_regs[1] = random.randint(0, (1 << 64)-1)
 119             self.run_tst_program(Program(lst), initial_regs)
 120
 121     def test_popcnt_edge(self):
 122         insns = ["popcntb", "popcntw", "popcntd"]
 123         for choice in insns:
 124             lst = [f"{choice} 3, 1"]
 125             initial_regs = [0] * 32
 126             initial_regs[1] = -1
 127             self.run_tst_program(Program(lst), initial_regs)
 128
 129     def test_cmpb(self):
 130         lst = ["cmpb 3, 1, 2"]
 131         initial_regs = [0] * 32
 132         initial_regs[1] = 0xdeadbeefcafec0de
 133         initial_regs[2] = 0xd0adb0000afec1de
 134         self.run_tst_program(Program(lst), initial_regs)
 135
 136     def test_bpermd(self):
 137         lst = ["bpermd 3, 1, 2"]
 138         for i in range(20):
 139             initial_regs = [0] * 32
 140             initial_regs[1] = 1<<random.randint(0,63)
 141             initial_regs[2] = 0xdeadbeefcafec0de
 142             self.run_tst_program(Program(lst), initial_regs)
 143
 144     def test_ilang(self):
 145         pspec = LogicalPipeSpec(id_wid=2)
 146         alu = LogicalBasePipe(pspec)
 147         vl = rtlil.convert(alu, ports=alu.ports())
 148         with open("logical_pipeline.il", "w") as f:
 149             f.write(vl)
 150
 151
 152 class TestRunner(FHDLTestCase):
 153     def __init__(self, test_data):
 154         super().__init__("run_all")
 155         self.test_data = test_data
 156
 157     def run_all(self):
 158         m = Module()
 159         comb = m.d.comb
 160         instruction = Signal(32)
 161
 162         pdecode = create_pdecode()
 163
 164         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 165
 166         pspec = LogicalPipeSpec(id_wid=2)
 167         m.submodules.alu = alu = LogicalBasePipe(pspec)
 168
 169         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 170         comb += alu.p.valid_i.eq(1)
 171         comb += alu.n.ready_i.eq(1)
 172         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 173         sim = Simulator(m)
 174
 175         sim.add_clock(1e-6)
 176
 177         def process():
 178             for test in self.test_data:
 179                 print(test.name)
 180                 program = test.program
 181                 self.subTest(test.name)
 182                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
 183                                 test.mem, test.msr)
 184                 gen = program.generate_instructions()
 185                 instructions = list(zip(gen, program.assembly.splitlines()))
 186
 187                 index = simulator.pc.CIA.value//4
 188                 while index < len(instructions):
 189                     ins, code = instructions[index]
 190
 191                     print("0x{:X}".format(ins & 0xffffffff))
 192                     print(code)
 193
 194                     # ask the decoder to decode this binary data (endian'd)
 195                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 196                     yield instruction.eq(ins)          # raw binary instr.
 197                     yield Settle()
 198                     fn_unit = yield pdecode2.e.fn_unit
 199                     self.assertEqual(fn_unit, Function.LOGICAL.value, code)
 200                     yield from set_alu_inputs(alu, pdecode2, simulator)
 201                     yield
 202                     opname = code.split(' ')[0]
 203                     yield from simulator.call(opname)
 204                     index = simulator.pc.CIA.value//4
 205
 206                     vld = yield alu.n.valid_o
 207                     while not vld:
 208                         yield
 209                         vld = yield alu.n.valid_o
 210                     yield
 211
 212                     yield from self.check_alu_outputs(alu, pdecode2,
 213                                                       simulator, code)
 214
 215         sim.add_sync_process(process)
 216         with sim.write_vcd("logical_simulator.vcd", "logical_simulator.gtkw",
 217                            traces=[]):
 218             sim.run()
 219
 220     def check_alu_outputs(self, alu, dec2, sim, code):
 221
 222         rc = yield dec2.e.rc.data
 223         cridx_ok = yield dec2.e.write_cr.ok
 224         cridx = yield dec2.e.write_cr.data
 225
 226         print ("check extra output", repr(code), cridx_ok, cridx)
 227         if rc:
 228             self.assertEqual(cridx, 0, code)
 229
 230         sim_o = {}
 231         res = {}
 232
 233         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 234         yield from ALUHelpers.get_int_o(res, alu, dec2)
 235
 236         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 237         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 238
 239         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 240         ALUHelpers.check_int_o(self, res, sim_o, code)
 241
 242
 243 if __name__ == "__main__":
 244     unittest.main(exit=False)
 245     suite = unittest.TestSuite()
 246     suite.addTest(TestRunner(LogicalTestCase.test_data))
 247
 248     runner = unittest.TextTestRunner()
 249     runner.run(suite)