src/soc/fu/logical/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.logical.pipeline import LogicalBasePipe
  16 from soc.fu.alu.alu_input_record import CompALUOpSubset
  17 from soc.fu.alu.pipe_data import ALUPipeSpec
  18 import random
  19
  20
  21 class TestCase:
  22     def __init__(self, program, regs, sprs, name):
  23         self.program = program
  24         self.regs = regs
  25         self.sprs = sprs
  26         self.name = name
  27
  28 def get_rec_width(rec):
  29     recwidth = 0
  30     # Setup random inputs for dut.op
  31     for p in rec.ports():
  32         width = p.width
  33         recwidth += width
  34     return recwidth
  35
  36 def set_alu_inputs(alu, dec2, sim):
  37     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  38     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  39     # and place it into data_i.b
  40
  41     reg3_ok = yield dec2.e.read_reg3.ok
  42     reg1_ok = yield dec2.e.read_reg1.ok
  43     assert reg3_ok != reg1_ok
  44     if reg3_ok:
  45         data1 = yield dec2.e.read_reg3.data
  46         data1 = sim.gpr(data1).value
  47     elif reg1_ok:
  48         data1 = yield dec2.e.read_reg1.data
  49         data1 = sim.gpr(data1).value
  50     else:
  51         data1 = 0
  52
  53     yield alu.p.data_i.a.eq(data1)
  54
  55     # If there's an immediate, set the B operand to that
  56     reg2_ok = yield dec2.e.read_reg2.ok
  57     imm_ok = yield dec2.e.imm_data.imm_ok
  58     if imm_ok:
  59         data2 = yield dec2.e.imm_data.imm
  60     elif reg2_ok:
  61         data2 = yield dec2.e.read_reg2.data
  62         data2 = sim.gpr(data2).value
  63     else:
  64         data2 = 0
  65     yield alu.p.data_i.b.eq(data2)
  66
  67
  68
  69 def set_extra_alu_inputs(alu, dec2, sim):
  70     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  71     carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  72     yield alu.p.data_i.xer_ca[0].eq(carry)
  73     yield alu.p.data_i.xer_ca[1].eq(carry32)
  74     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  75     yield alu.p.data_i.xer_so.eq(so)
  76
  77
  78 # This test bench is a bit different than is usual. Initially when I
  79 # was writing it, I had all of the tests call a function to create a
  80 # device under test and simulator, initialize the dut, run the
  81 # simulation for ~2 cycles, and assert that the dut output what it
  82 # should have. However, this was really slow, since it needed to
  83 # create and tear down the dut and simulator for every test case.
  84
  85 # Now, instead of doing that, every test case in ALUTestCase puts some
  86 # data into the test_data list below, describing the instructions to
  87 # be tested and the initial state. Once all the tests have been run,
  88 # test_data gets passed to TestRunner which then sets up the DUT and
  89 # simulator once, runs all the data through it, and asserts that the
  90 # results match the pseudocode sim at every cycle.
  91
  92 # By doing this, I've reduced the time it takes to run the test suite
  93 # massively. Before, it took around 1 minute on my computer, now it
  94 # takes around 3 seconds
  95
  96 test_data = []
  97
  98
  99 class LogicalTestCase(FHDLTestCase):
 100     def __init__(self, name):
 101         super().__init__(name)
 102         self.test_name = name
 103     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
 104         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
 105         test_data.append(tc)
 106
 107     def test_rand(self):
 108         insns = ["and", "or", "xor"]
 109         for i in range(40):
 110             choice = random.choice(insns)
 111             lst = [f"{choice} 3, 1, 2"]
 112             initial_regs = [0] * 32
 113             initial_regs[1] = random.randint(0, (1<<64)-1)
 114             initial_regs[2] = random.randint(0, (1<<64)-1)
 115             self.run_tst_program(Program(lst), initial_regs)
 116
 117     def test_rand_imm_logical(self):
 118         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
 119         for i in range(10):
 120             choice = random.choice(insns)
 121             imm = random.randint(0, (1<<16)-1)
 122             lst = [f"{choice} 3, 1, {imm}"]
 123             print(lst)
 124             initial_regs = [0] * 32
 125             initial_regs[1] = random.randint(0, (1<<64)-1)
 126             self.run_tst_program(Program(lst), initial_regs)
 127
 128     def test_cntz(self):
 129         insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
 130         for i in range(100):
 131             choice = random.choice(insns)
 132             lst = [f"{choice} 3, 1"]
 133             print(lst)
 134             initial_regs = [0] * 32
 135             initial_regs[1] = random.randint(0, (1<<64)-1)
 136             self.run_tst_program(Program(lst), initial_regs)
 137
 138     def test_parity(self):
 139         insns = ["prtyw", "prtyd"]
 140         for i in range(10):
 141             choice = random.choice(insns)
 142             lst = [f"{choice} 3, 1"]
 143             print(lst)
 144             initial_regs = [0] * 32
 145             initial_regs[1] = random.randint(0, (1<<64)-1)
 146             self.run_tst_program(Program(lst), initial_regs)
 147
 148     def test_popcnt(self):
 149         insns = ["popcntb", "popcntw", "popcntd"]
 150         for i in range(10):
 151             choice = random.choice(insns)
 152             lst = [f"{choice} 3, 1"]
 153             print(lst)
 154             initial_regs = [0] * 32
 155             initial_regs[1] = random.randint(0, (1<<64)-1)
 156             self.run_tst_program(Program(lst), initial_regs)
 157
 158     def test_popcnt_edge(self):
 159         insns = ["popcntb", "popcntw", "popcntd"]
 160         for choice in insns:
 161             lst = [f"{choice} 3, 1"]
 162             initial_regs = [0] * 32
 163             initial_regs[1] = -1
 164             self.run_tst_program(Program(lst), initial_regs)
 165
 166     def test_cmpb(self):
 167         lst = ["cmpb 3, 1, 2"]
 168         initial_regs = [0] * 32
 169         initial_regs[1] = 0xdeadbeefcafec0de
 170         initial_regs[2] = 0xd0adb0000afec1de
 171         self.run_tst_program(Program(lst), initial_regs)
 172
 173     def test_ilang(self):
 174         rec = CompALUOpSubset()
 175
 176         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
 177         alu = LogicalBasePipe(pspec)
 178         vl = rtlil.convert(alu, ports=alu.ports())
 179         with open("logical_pipeline.il", "w") as f:
 180             f.write(vl)
 181
 182
 183 class TestRunner(FHDLTestCase):
 184     def __init__(self, test_data):
 185         super().__init__("run_all")
 186         self.test_data = test_data
 187
 188     def run_all(self):
 189         m = Module()
 190         comb = m.d.comb
 191         instruction = Signal(32)
 192
 193         pdecode = create_pdecode()
 194
 195         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 196
 197         rec = CompALUOpSubset()
 198
 199         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
 200         m.submodules.alu = alu = LogicalBasePipe(pspec)
 201
 202         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 203         comb += alu.p.valid_i.eq(1)
 204         comb += alu.n.ready_i.eq(1)
 205         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 206         sim = Simulator(m)
 207
 208         sim.add_clock(1e-6)
 209         def process():
 210             for test in self.test_data:
 211                 print(test.name)
 212                 program = test.program
 213                 self.subTest(test.name)
 214                 simulator = ISA(pdecode2, test.regs, test.sprs, 0)
 215                 gen = program.generate_instructions()
 216                 instructions = list(zip(gen, program.assembly.splitlines()))
 217
 218                 index = simulator.pc.CIA.value//4
 219                 while index < len(instructions):
 220                     ins, code = instructions[index]
 221
 222                     print("0x{:X}".format(ins & 0xffffffff))
 223                     print(code)
 224
 225                     # ask the decoder to decode this binary data (endian'd)
 226                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 227                     yield instruction.eq(ins)          # raw binary instr.
 228                     yield Settle()
 229                     fn_unit = yield pdecode2.e.fn_unit
 230                     self.assertEqual(fn_unit, Function.LOGICAL.value, code)
 231                     yield from set_alu_inputs(alu, pdecode2, simulator)
 232                     yield from set_extra_alu_inputs(alu, pdecode2, simulator)
 233                     yield
 234                     opname = code.split(' ')[0]
 235                     yield from simulator.call(opname)
 236                     index = simulator.pc.CIA.value//4
 237
 238                     vld = yield alu.n.valid_o
 239                     while not vld:
 240                         yield
 241                         vld = yield alu.n.valid_o
 242                     yield
 243                     alu_out = yield alu.n.data_o.o
 244                     out_reg_valid = yield pdecode2.e.write_reg.ok
 245                     if out_reg_valid:
 246                         write_reg_idx = yield pdecode2.e.write_reg.data
 247                         expected = simulator.gpr(write_reg_idx).value
 248                         print(f"expected {expected:x}, actual: {alu_out:x}")
 249                         self.assertEqual(expected, alu_out, code)
 250                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 251                                                             simulator, code)
 252
 253         sim.add_sync_process(process)
 254         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 255                             traces=[]):
 256             sim.run()
 257     def check_extra_alu_outputs(self, alu, dec2, sim, code):
 258         rc = yield dec2.e.rc.data
 259         if rc:
 260             cr_expected = sim.crl[0].get_range().value
 261             cr_actual = yield alu.n.data_o.cr0.data
 262             self.assertEqual(cr_expected, cr_actual, code)
 263
 264
 265 if __name__ == "__main__":
 266     unittest.main(exit=False)
 267     suite = unittest.TestSuite()
 268     suite.addTest(TestRunner(test_data))
 269
 270     runner = unittest.TextTestRunner()
 271     runner.run(suite)