src/soc/fu/logical/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2
   3 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   4 # Also, check out the cxxsim nmigen branch, and latest yosys from git
   5 from nmutil.sim_tmp_alternative import Simulator, Settle
   6
   7 from nmutil.formaltest import FHDLTestCase
   8 from nmigen.cli import rtlil
   9 import unittest
  10 from openpower.decoder.power_decoder import create_pdecode
  11 from openpower.decoder.power_decoder2 import PowerDecode2
  12 from openpower.decoder.power_enums import (XER_bits, Function)
  13 from openpower.decoder.isa.all import ISA
  14 from openpower.endian import bigendian
  15
  16
  17 from openpower.test.common import TestAccumulatorBase, ALUHelpers
  18 from soc.fu.logical.pipeline import LogicalBasePipe
  19 from soc.fu.logical.pipe_data import LogicalPipeSpec
  20 import random
  21
  22 from openpower.test.logical.logical_cases import LogicalTestCase
  23
  24
  25 def get_cu_inputs(dec2, sim):
  26     """naming (res) must conform to LogicalFunctionUnit input regspec
  27     """
  28     res = {}
  29
  30     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  31     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  32     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  33
  34     print("alu get_cu_inputs", res)
  35
  36     return res
  37
  38
  39 def set_alu_inputs(alu, dec2, sim):
  40     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  41     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  42     # and place it into i_data.b
  43
  44     inp = yield from get_cu_inputs(dec2, sim)
  45     print("set alu inputs", inp)
  46     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  47     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  48     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  49
  50
  51 class LogicalIlangCase(TestAccumulatorBase):
  52
  53     def case_ilang(self):
  54         pspec = LogicalPipeSpec(id_wid=2, parent_pspec=None)
  55         alu = LogicalBasePipe(pspec)
  56         vl = rtlil.convert(alu, ports=alu.ports())
  57         with open("logical_pipeline.il", "w") as f:
  58             f.write(vl)
  59
  60
  61 class TestRunner(FHDLTestCase):
  62     def __init__(self, test_data):
  63         super().__init__("run_all")
  64         self.test_data = test_data
  65
  66     def execute(self, alu, instruction, pdecode2, test):
  67         print(test.name)
  68         program = test.program
  69         self.subTest(test.name)
  70         simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
  71                         test.mem, test.msr,
  72                         bigendian=bigendian)
  73         gen = program.generate_instructions()
  74         instructions = list(zip(gen, program.assembly.splitlines()))
  75
  76         index = simulator.pc.CIA.value//4
  77         while index < len(instructions):
  78             ins, code = instructions[index]
  79
  80             print("0x{:X}".format(ins & 0xffffffff))
  81             print(code)
  82
  83             # ask the decoder to decode this binary data (endian'd)
  84             yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
  85             yield instruction.eq(ins)          # raw binary instr.
  86             yield Settle()
  87             fn_unit = yield pdecode2.e.do.fn_unit
  88             self.assertEqual(fn_unit, Function.LOGICAL.value, code)
  89             yield from set_alu_inputs(alu, pdecode2, simulator)
  90
  91             # set valid for one cycle, propagate through pipeline...
  92             yield alu.p.i_valid.eq(1)
  93             yield
  94             yield alu.p.i_valid.eq(0)
  95
  96             opname = code.split(' ')[0]
  97             yield from simulator.call(opname)
  98             index = simulator.pc.CIA.value//4
  99
 100             vld = yield alu.n.o_valid
 101             while not vld:
 102                 yield
 103                 vld = yield alu.n.o_valid
 104             yield
 105
 106             yield from self.check_alu_outputs(alu, pdecode2,
 107                                               simulator, code)
 108             yield Settle()
 109
 110     def run_all(self):
 111         m = Module()
 112         comb = m.d.comb
 113         instruction = Signal(32)
 114
 115         pdecode = create_pdecode()
 116
 117         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 118
 119         pspec = LogicalPipeSpec(id_wid=2, parent_pspec=None)
 120         m.submodules.alu = alu = LogicalBasePipe(pspec)
 121
 122         comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
 123         comb += alu.n.i_ready.eq(1)
 124         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 125         sim = Simulator(m)
 126
 127         sim.add_clock(1e-6)
 128
 129         def process():
 130             for test in self.test_data:
 131                 print(test.name)
 132                 program = test.program
 133                 with self.subTest(test.name):
 134                     yield from self.execute(alu, instruction, pdecode2, test)
 135
 136         sim.add_sync_process(process)
 137         with sim.write_vcd("logical_simulator.vcd", "logical_simulator.gtkw",
 138                            traces=[]):
 139             sim.run()
 140
 141     def check_alu_outputs(self, alu, dec2, sim, code):
 142
 143         rc = yield dec2.e.do.rc.data
 144         cridx_ok = yield dec2.e.write_cr.ok
 145         cridx = yield dec2.e.write_cr.data
 146
 147         print("check extra output", repr(code), cridx_ok, cridx)
 148         if rc:
 149             self.assertEqual(cridx, 0, code)
 150
 151         sim_o = {}
 152         res = {}
 153
 154         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 155         yield from ALUHelpers.get_int_o(res, alu, dec2)
 156
 157         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 158         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 159
 160         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 161         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 162         ALUHelpers.check_int_o(self, res, sim_o, code)
 163
 164
 165 if __name__ == "__main__":
 166     unittest.main(exit=False)
 167     suite = unittest.TestSuite()
 168     suite.addTest(TestRunner(LogicalIlangCase().test_data))
 169     suite.addTest(TestRunner(LogicalTestCase().test_data))
 170
 171     runner = unittest.TextTestRunner()
 172     runner.run(suite)