split out front of div into separate stage, still too long combinatorial
[soc.git] / src / soc / fu / logical / test / test_pipe_caller.py
1 from nmigen import Module, Signal
2
3 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
4 # Also, check out the cxxsim nmigen branch, and latest yosys from git
5 from nmutil.sim_tmp_alternative import Simulator, Settle
6
7 from nmutil.formaltest import FHDLTestCase
8 from nmigen.cli import rtlil
9 import unittest
10 from openpower.decoder.power_decoder import create_pdecode
11 from openpower.decoder.power_decoder2 import PowerDecode2
12 from openpower.decoder.power_enums import (XER_bits, Function)
13 from openpower.decoder.isa.all import ISA
14 from openpower.endian import bigendian
15
16
17 from openpower.test.common import TestAccumulatorBase, ALUHelpers
18 from soc.fu.logical.pipeline import LogicalBasePipe
19 from soc.fu.logical.pipe_data import LogicalPipeSpec
20 import random
21
22 from openpower.test.logical.logical_cases import LogicalTestCase
23
24
25 def get_cu_inputs(dec2, sim):
26 """naming (res) must conform to LogicalFunctionUnit input regspec
27 """
28 res = {}
29
30 yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
31 yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
32 yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
33
34 print("alu get_cu_inputs", res)
35
36 return res
37
38
39 def set_alu_inputs(alu, dec2, sim):
40 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
41 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
42 # and place it into i_data.b
43
44 inp = yield from get_cu_inputs(dec2, sim)
45 print("set alu inputs", inp)
46 yield from ALUHelpers.set_int_ra(alu, dec2, inp)
47 yield from ALUHelpers.set_int_rb(alu, dec2, inp)
48 yield from ALUHelpers.set_xer_so(alu, dec2, inp)
49
50
51 class LogicalIlangCase(TestAccumulatorBase):
52
53 def case_ilang(self):
54 class PPspec:
55 XLEN = 64
56 pps = PPspec()
57 pspec = LogicalPipeSpec(id_wid=2, parent_pspec=pps)
58 alu = LogicalBasePipe(pspec)
59 vl = rtlil.convert(alu, ports=alu.ports())
60 with open("logical_pipeline.il", "w") as f:
61 f.write(vl)
62
63
64 class TestRunner(unittest.TestCase):
65
66 def execute(self, alu, instruction, pdecode2, test):
67 print(test.name)
68 program = test.program
69 self.subTest(test.name)
70 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
71 test.mem, test.msr,
72 bigendian=bigendian)
73 gen = program.generate_instructions()
74 instructions = list(zip(gen, program.assembly.splitlines()))
75
76 index = simulator.pc.CIA.value//4
77 while index < len(instructions):
78 ins, code = instructions[index]
79
80 print("0x{:X}".format(ins & 0xffffffff))
81 print(code)
82
83 # ask the decoder to decode this binary data (endian'd)
84 yield pdecode2.dec.bigendian.eq(bigendian) # little / big?
85 yield instruction.eq(ins) # raw binary instr.
86 yield Settle()
87 fn_unit = yield pdecode2.e.do.fn_unit
88 self.assertEqual(fn_unit, Function.LOGICAL.value, code)
89 yield from set_alu_inputs(alu, pdecode2, simulator)
90
91 # set valid for one cycle, propagate through pipeline...
92 yield alu.p.i_valid.eq(1)
93 yield
94 yield alu.p.i_valid.eq(0)
95
96 opname = code.split(' ')[0]
97 yield from simulator.call(opname)
98 index = simulator.pc.CIA.value//4
99
100 vld = yield alu.n.o_valid
101 while not vld:
102 yield
103 vld = yield alu.n.o_valid
104 yield
105
106 yield from self.check_alu_outputs(alu, pdecode2,
107 simulator, code)
108 yield Settle()
109
110 def test_it(self):
111 test_data = LogicalIlangCase().test_data + \
112 LogicalTestCase().test_data
113 m = Module()
114 comb = m.d.comb
115 instruction = Signal(32)
116
117 pdecode = create_pdecode()
118
119 m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
120
121 class PPspec:
122 XLEN = 64
123 pps = PPspec()
124 pspec = LogicalPipeSpec(id_wid=2, parent_pspec=pps)
125 m.submodules.alu = alu = LogicalBasePipe(pspec)
126
127 comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
128 comb += alu.n.i_ready.eq(1)
129 comb += pdecode2.dec.raw_opcode_in.eq(instruction)
130 sim = Simulator(m)
131
132 sim.add_clock(1e-6)
133
134 def process():
135 for test in test_data:
136 print(test.name)
137 program = test.program
138 with self.subTest(test.name):
139 yield from self.execute(alu, instruction, pdecode2, test)
140
141 sim.add_sync_process(process)
142 with sim.write_vcd("logical_simulator.vcd", "logical_simulator.gtkw",
143 traces=[]):
144 sim.run()
145
146 def check_alu_outputs(self, alu, dec2, sim, code):
147
148 rc = yield dec2.e.do.rc.data
149 cridx_ok = yield dec2.e.write_cr.ok
150 cridx = yield dec2.e.write_cr.data
151
152 print("check extra output", repr(code), cridx_ok, cridx)
153 if rc:
154 self.assertEqual(cridx, 0, code)
155
156 sim_o = {}
157 res = {}
158
159 yield from ALUHelpers.get_cr_a(res, alu, dec2)
160 yield from ALUHelpers.get_int_o(res, alu, dec2)
161
162 yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
163 yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
164
165 ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
166 ALUHelpers.check_xer_ca(self, res, sim_o, code)
167 ALUHelpers.check_int_o(self, res, sim_o, code)
168
169
170 if __name__ == "__main__":
171 unittest.main()