src/soc/fu/mmu/fsm.py

   1 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
   2 from nmigen import Const
   3 from soc.fu.mmu.pipe_data import MMUInputData, MMUOutputData, MMUPipeSpec
   4 from nmutil.singlepipe import ControlBase
   5 from nmutil.util import rising_edge
   6
   7 from soc.experiment.mmu import MMU
   8 from soc.experiment.dcache import DCache
   9
  10 from soc.decoder.power_fields import DecodeFields
  11 from soc.decoder.power_fieldsn import SignalBitRange
  12 from soc.decoder.power_decoder2 import decode_spr_num
  13 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
  14
  15 from soc.experiment.pimem import PortInterface
  16 from soc.experiment.pimem import PortInterfaceBase
  17
  18 from soc.experiment.mem_types import LoadStore1ToDCacheType, LoadStore1ToMMUType
  19 from soc.experiment.mem_types import DCacheToLoadStore1Type, MMUToLoadStore1Type
  20
  21 # for testing purposes
  22 from soc.experiment.testmem import TestMemory
  23
  24 # glue logic for microwatt mmu and dcache
  25 class LoadStore1(PortInterfaceBase):
  26     def __init__(self, regwid=64, addrwid=4):
  27         super().__init__(regwid, addrwid)
  28         self.d_in  = LoadStore1ToDCacheType()
  29         self.d_out = DCacheToLoadStore1Type()
  30         self.l_in  = LoadStore1ToMMUType()
  31         self.l_out = MMUToLoadStore1Type()
  32         # for debugging with gtkwave only
  33         self.debug1 = Signal()
  34         self.debug2 = Signal()
  35
  36     def set_wr_addr(self, m, addr, mask):
  37         #m.d.comb += self.d_in.valid.eq(1)
  38         #m.d.comb += self.l_in.valid.eq(1)
  39         #m.d.comb += self.d_in.load.eq(0)
  40         #m.d.comb += self.l_in.load.eq(0)
  41         m.d.comb += self.d_in.addr.eq(addr)
  42         m.d.comb += self.l_in.addr.eq(addr)
  43         # TODO set mask
  44         return None
  45
  46     def set_rd_addr(self, m, addr, mask):
  47         m.d.comb += self.d_in.valid.eq(1)
  48         m.d.comb += self.l_in.valid.eq(1)
  49         m.d.comb += self.d_in.load.eq(1)
  50         m.d.comb += self.l_in.load.eq(1)
  51         m.d.comb += self.d_in.addr.eq(addr)
  52         m.d.comb += self.l_in.addr.eq(addr)
  53         m.d.comb += self.debug1.eq(1)
  54         # m.d.comb += self.debug2.eq(1)
  55         # connect testmem first
  56         return None #FIXME return value
  57
  58     def set_wr_data(self, m, data, wen):
  59         m.d.comb += self.d_in.data.eq(data)
  60         # TODO set wen
  61         st_ok = Const(1, 1)
  62         return st_ok
  63
  64     def get_rd_data(self, m):
  65         ld_ok = Const(1, 1)
  66         data = self.d_out.data
  67         return data, ld_ok
  68
  69     def elaborate(self, platform):
  70         m = super().elaborate(platform)
  71
  72         d_out = self.d_out
  73         l_out = self.l_out
  74
  75         exc = self.pi.exception_o
  76
  77         #happened, alignment, instr_fault, invalid,
  78         m.d.comb += exc.happened.eq(d_out.error | l_out.err)
  79         m.d.comb += exc.invalid.eq(l_out.invalid)
  80
  81         #badtree, perm_error, rc_error, segment_fault
  82         m.d.comb += exc.badtree.eq(l_out.badtree)
  83         m.d.comb += exc.perm_error.eq(l_out.perm_error)
  84         m.d.comb += exc.rc_error.eq(l_out.rc_error)
  85         m.d.comb += exc.segment_fault.eq(l_out.segerr)
  86
  87         # TODO connect those signals somewhere
  88         #print(d_out.valid)         -> no error
  89         #print(d_out.store_done)    -> no error
  90         #print(d_out.cache_paradox) -> ?
  91         #print(l_out.done)          -> no error
  92
  93         # TODO some exceptions set SPRs
  94
  95         return m
  96
  97     def ports(self):
  98         yield from super().ports()
  99         # TODO: memory ports
 100
 101 class FSMMMUStage(ControlBase):
 102     def __init__(self, pspec):
 103         super().__init__()
 104         self.pspec = pspec
 105
 106         # set up p/n data
 107         self.p.data_i = MMUInputData(pspec)
 108         self.n.data_o = MMUOutputData(pspec)
 109
 110         # incoming PortInterface
 111         self.ldst = LoadStore1()       # TODO make this depend on pspec
 112         self.pi = self.ldst.pi
 113
 114         # this Function Unit is extremely unusual in that it actually stores a
 115         # "thing" rather than "processes inputs and produces outputs".  hence
 116         # why it has to be a FSM.  linking up LD/ST however is going to have
 117         # to be done back in Issuer (or Core)
 118
 119         self.mmu = MMU()
 120         self.dcache = DCache()
 121         regwid=64
 122         aw = 5
 123         # for verification of DCache
 124         # TODO: create connection to real memory, backend memory interface
 125         self.testmem = TestMemory(regwid, aw, granularity=regwid//8, init=False)
 126
 127         # make life a bit easier in Core
 128         self.pspec.mmu = self.mmu
 129         self.pspec.dcache = self.dcache
 130
 131         # debugging output for gtkw
 132         self.debug0 = Signal(4)
 133         self.debug_wb_cyc = Signal()
 134         self.debug_wb_stb = Signal()
 135         self.debug_wb_we = Signal()
 136         #self.debug1 = Signal(64)
 137         #self.debug2 = Signal(64)
 138         #self.debug3 = Signal(64)
 139
 140         # for SPR field number access
 141         i = self.p.data_i
 142         self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
 143         self.fields.create_specs()
 144
 145     def elaborate(self, platform):
 146         m = super().elaborate(platform)
 147         comb = m.d.comb
 148
 149         # link mmu and dcache together
 150         m.submodules.dcache = dcache = self.dcache
 151         m.submodules.mmu = mmu = self.mmu
 152         m.submodules.ldst = ldst = self.ldst
 153         m.submodules.testmem = testmem = self.testmem
 154         m.d.comb += dcache.m_in.eq(mmu.d_out)
 155         m.d.comb += mmu.d_in.eq(dcache.m_out)
 156         l_in, l_out = mmu.l_in, mmu.l_out
 157         d_in, d_out = dcache.d_in, dcache.d_out
 158         wb_out, wb_in = dcache.wb_out, dcache.wb_in
 159
 160         # link ldst and dcache together
 161         comb += l_in.eq(self.ldst.l_in)
 162         comb += self.ldst.l_out.eq(l_out)
 163         comb += d_in.eq(self.ldst.d_in)
 164         comb += self.ldst.d_out.eq(self.dcache.d_out)
 165
 166         #connect read port
 167         rdport = self.testmem.rdport
 168         comb += rdport.addr.eq(wb_out.adr)
 169         comb += wb_in.dat.eq(rdport.data)
 170
 171         #connect write port
 172         wrport = self.testmem.wrport
 173         comb += wrport.addr.eq(wb_out.adr)
 174         comb += wrport.data.eq(wb_out.dat) # write st to mem
 175         comb += wrport.en.eq(wb_out.cyc & wb_out.we) # enable writes
 176
 177         # connect DCache wishbone master to debugger
 178         comb += self.debug_wb_cyc.eq(wb_out.cyc)
 179         comb += self.debug_wb_stb.eq(wb_out.stb)
 180         comb += self.debug_wb_we.eq(wb_out.we)
 181
 182         comb += wb_in.stall.eq(0)
 183         # testmem only takes on cycle
 184         with m.If( wb_out.cyc ):
 185             m.d.sync += wb_in.ack.eq( wb_out.stb )
 186
 187         data_i, data_o = self.p.data_i, self.n.data_o
 188         a_i, b_i, o = data_i.ra, data_i.rb, data_o.o
 189         op = data_i.ctx.op
 190
 191         # TODO: link these SPRs somewhere
 192         dsisr = Signal(64)
 193         dar = Signal(64)
 194
 195         # busy/done signals
 196         busy = Signal()
 197         done = Signal()
 198         m.d.comb += self.n.valid_o.eq(busy & done)
 199         m.d.comb += self.p.ready_o.eq(~busy)
 200
 201         # take copy of X-Form SPR field
 202         x_fields = self.fields.FormXFX
 203         spr = Signal(len(x_fields.SPR))
 204         comb += spr.eq(decode_spr_num(x_fields.SPR))
 205
 206         # ok so we have to "pulse" the MMU (or dcache) rather than
 207         # hold the valid hi permanently.  guess what this does...
 208         valid = Signal()
 209         blip = Signal()
 210         m.d.comb += blip.eq(rising_edge(m, valid))
 211
 212         with m.If(~busy):
 213             with m.If(self.p.valid_i):
 214                 m.d.sync += busy.eq(1)
 215         with m.Else():
 216
 217             # based on the Micro-Op, we work out which of MMU or DCache
 218             # should "action" the operation.  one of MMU or DCache gets
 219             # enabled ("valid") and we twiddle our thumbs until it
 220             # responds ("done").
 221
 222             # FIXME: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
 223
 224             with m.Switch(op.insn_type):
 225                 comb += self.debug0.eq(3)
 226                 with m.Case(MicrOp.OP_MTSPR):
 227                     # subset SPR: first check a few bits
 228                     with m.If(~spr[9] & ~spr[5]):
 229                         with m.If(spr[0]):
 230                             comb += dsisr.eq(a_i[:32])
 231                         with m.Else():
 232                             comb += dar.eq(a_i)
 233                         comb += done.eq(1)
 234                     # pass it over to the MMU instead
 235                     with m.Else():
 236                         # blip the MMU and wait for it to complete
 237                         comb += valid.eq(1)   # start "pulse"
 238                         comb += l_in.valid.eq(blip)   # start
 239                         comb += l_in.mtspr.eq(1)      # mtspr mode
 240                         comb += l_in.sprn.eq(spr)  # which SPR
 241                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 242                         comb += done.eq(l_out.done) # zzzz
 243
 244                 with m.Case(MicrOp.OP_MFSPR):
 245                     comb += self.debug0.eq(3)
 246                     # subset SPR: first check a few bits
 247                     with m.If(~spr[9] & ~spr[5]):
 248                         with m.If(spr[0]):
 249                             comb += o.data.eq(dsisr)
 250                         with m.Else():
 251                             comb += o.data.eq(dar)
 252                         comb += o.ok.eq(1)
 253                         comb += done.eq(1)
 254                     # pass it over to the MMU instead
 255                     with m.Else():
 256                         # blip the MMU and wait for it to complete
 257                         comb += valid.eq(1)   # start "pulse"
 258                         comb += l_in.valid.eq(blip)   # start
 259                         comb += l_in.mtspr.eq(0)   # mfspr!=mtspr
 260                         comb += l_in.sprn.eq(spr)  # which SPR
 261                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 262                         comb += o.data.eq(l_out.sprval) # SPR from MMU
 263                         comb += o.ok.eq(l_out.done) # only when l_out valid
 264                         comb += done.eq(l_out.done) # zzzz
 265
 266                 with m.Case(MicrOp.OP_DCBZ):
 267                     # activate dcbz mode (spec: v3.0B p850)
 268                     comb += valid.eq(1)   # start "pulse"
 269                     comb += d_in.valid.eq(blip)     # start
 270                     comb += d_in.dcbz.eq(1)         # dcbz mode
 271                     comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
 272                     comb += done.eq(d_out.store_done)     # TODO
 273                     comb += self.debug0.eq(1)
 274
 275                 with m.Case(MicrOp.OP_TLBIE):
 276                     # pass TLBIE request to MMU (spec: v3.0B p1034)
 277                     # note that the spr is *not* an actual spr number, it's
 278                     # just that those bits happen to match with field bits
 279                     # RIC, PRS, R
 280                     comb += valid.eq(1)   # start "pulse"
 281                     comb += l_in.valid.eq(blip)   # start
 282                     comb += l_in.tlbie.eq(1)   # mtspr mode
 283                     comb += l_in.sprn.eq(spr)  # use sprn to send insn bits
 284                     comb += l_in.addr.eq(b_i)  # incoming operand (RB)
 285                     comb += done.eq(l_out.done) # zzzz
 286                     comb += self.debug0.eq(2)
 287
 288             with m.If(self.n.ready_i & self.n.valid_o):
 289                 m.d.sync += busy.eq(0)
 290
 291         return m
 292
 293     def __iter__(self):
 294         yield from self.p
 295         yield from self.n
 296
 297     def ports(self):
 298         return list(self)