src/soc/fu/mmu/fsm.py

   1 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
   2 from nmigen import Const
   3 from soc.fu.mmu.pipe_data import MMUInputData, MMUOutputData, MMUPipeSpec
   4 from nmutil.singlepipe import ControlBase
   5 from nmutil.util import rising_edge
   6
   7 from soc.experiment.mmu import MMU
   8 from soc.experiment.dcache import DCache
   9
  10 from soc.decoder.power_fields import DecodeFields
  11 from soc.decoder.power_fieldsn import SignalBitRange
  12 from soc.decoder.power_decoder2 import decode_spr_num
  13 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
  14
  15 from soc.experiment.pimem import PortInterface
  16 from soc.experiment.pimem import PortInterfaceBase
  17
  18 from soc.experiment.mem_types import LoadStore1ToDCacheType, LoadStore1ToMMUType
  19 from soc.experiment.mem_types import DCacheToLoadStore1Type, MMUToLoadStore1Type
  20
  21 # for testing purposes
  22 from soc.experiment.testmem import TestMemory
  23
  24 # glue logic for microwatt mmu and dcache
  25 class LoadStore1(PortInterfaceBase):
  26     def __init__(self, regwid=64, addrwid=4):
  27         super().__init__(regwid, addrwid)
  28         self.d_in  = LoadStore1ToDCacheType()
  29         self.d_out = DCacheToLoadStore1Type()
  30         self.l_in  = LoadStore1ToMMUType()
  31         self.l_out = MMUToLoadStore1Type()
  32         # for debugging with gtkwave only
  33         self.debug1 = Signal()
  34         self.debug2 = Signal()
  35
  36     def set_wr_addr(self, m, addr, mask):
  37         #m.d.comb += self.d_in.valid.eq(1)
  38         #m.d.comb += self.l_in.valid.eq(1)
  39         #m.d.comb += self.d_in.load.eq(0)
  40         #m.d.comb += self.l_in.load.eq(0)
  41         m.d.comb += self.d_in.addr.eq(addr)
  42         m.d.comb += self.l_in.addr.eq(addr)
  43         # TODO set mask
  44         return None
  45
  46     def set_rd_addr(self, m, addr, mask):
  47         m.d.comb += self.d_in.valid.eq(1)
  48         m.d.comb += self.l_in.valid.eq(1)
  49         m.d.comb += self.d_in.load.eq(1)
  50         m.d.comb += self.l_in.load.eq(1)
  51         m.d.comb += self.d_in.addr.eq(addr)
  52         m.d.comb += self.l_in.addr.eq(addr)
  53         m.d.comb += self.debug1.eq(1)
  54         # m.d.comb += self.debug2.eq(1)
  55         # connect testmem first
  56         return None #FIXME return value
  57
  58     def set_wr_data(self, m, data, wen):
  59         m.d.comb += self.d_in.data.eq(data)
  60         # TODO set wen
  61         st_ok = Const(1, 1)
  62         return st_ok
  63
  64     def get_rd_data(self, m):
  65         ld_ok = Const(1, 1)
  66         data = self.d_out.data
  67         return data, ld_ok
  68
  69     def elaborate(self, platform):
  70         m = super().elaborate(platform)
  71         #TODO
  72
  73         return m
  74
  75     def ports(self):
  76         yield from super().ports()
  77         # TODO: memory ports
  78
  79 class FSMMMUStage(ControlBase):
  80     def __init__(self, pspec):
  81         super().__init__()
  82         self.pspec = pspec
  83
  84         # set up p/n data
  85         self.p.data_i = MMUInputData(pspec)
  86         self.n.data_o = MMUOutputData(pspec)
  87
  88         # incoming PortInterface
  89         self.ldst = LoadStore1()       # TODO make this depend on pspec
  90         self.pi = self.ldst.pi
  91
  92         # this Function Unit is extremely unusual in that it actually stores a
  93         # "thing" rather than "processes inputs and produces outputs".  hence
  94         # why it has to be a FSM.  linking up LD/ST however is going to have
  95         # to be done back in Issuer (or Core)
  96
  97         self.mmu = MMU()
  98         self.dcache = DCache()
  99         regwid=64
 100         aw = 5
 101         # for verification of DCache
 102         # XXX -- read testmem.py
 103         self.testmem = TestMemory(regwid, aw, granularity=regwid//8, init=False)
 104
 105         # make life a bit easier in Core
 106         self.pspec.mmu = self.mmu
 107         self.pspec.dcache = self.dcache
 108
 109         # debugging output for gtkw
 110         self.debug0 = Signal(4)
 111         self.debug_wb_cyc = Signal()
 112         self.debug_wb_stb = Signal()
 113         self.debug_wb_we = Signal()
 114         #self.debug1 = Signal(64)
 115         #self.debug2 = Signal(64)
 116         #self.debug3 = Signal(64)
 117
 118         # for SPR field number access
 119         i = self.p.data_i
 120         self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
 121         self.fields.create_specs()
 122
 123     def elaborate(self, platform):
 124         m = super().elaborate(platform)
 125         comb = m.d.comb
 126
 127         # link mmu and dcache together
 128         m.submodules.dcache = dcache = self.dcache
 129         m.submodules.mmu = mmu = self.mmu
 130         m.submodules.ldst = ldst = self.ldst
 131         m.submodules.testmem = testmem = self.testmem
 132         m.d.comb += dcache.m_in.eq(mmu.d_out)
 133         m.d.comb += mmu.d_in.eq(dcache.m_out)
 134         l_in, l_out = mmu.l_in, mmu.l_out
 135         d_in, d_out = dcache.d_in, dcache.d_out
 136         wb_out, wb_in = dcache.wb_out, dcache.wb_in
 137
 138         # link ldst and dcache together
 139         comb += l_in.eq(self.ldst.l_in)
 140         comb += self.ldst.l_out.eq(l_out)
 141         comb += d_in.eq(self.ldst.d_in)
 142         comb += self.ldst.d_out.eq(self.dcache.d_out)
 143
 144         #connect read port
 145         rdport = self.testmem.rdport
 146         comb += rdport.addr.eq(wb_out.adr)
 147         comb += wb_in.dat.eq(rdport.data)
 148
 149         #connect write port
 150         wrport = self.testmem.wrport
 151         comb += wrport.addr.eq(wb_out.adr)
 152         comb += wrport.data.eq(wb_out.dat) # write st to mem
 153         comb += wrport.en.eq(wb_out.cyc & wb_out.we) # enable writes
 154
 155         # connect DCache wishbone master to debugger
 156         comb += self.debug_wb_cyc.eq(wb_out.cyc)
 157         comb += self.debug_wb_stb.eq(wb_out.stb)
 158         comb += self.debug_wb_we.eq(wb_out.we)
 159
 160         comb += wb_in.stall.eq(0)
 161         # testmem only takes on cycle
 162         with m.If( wb_out.cyc ):
 163             m.d.sync += wb_in.ack.eq( wb_out.stb )
 164
 165         data_i, data_o = self.p.data_i, self.n.data_o
 166         a_i, b_i, o = data_i.ra, data_i.rb, data_o.o
 167         op = data_i.ctx.op
 168
 169         # TODO: link these SPRs somewhere
 170         dsisr = Signal(64)
 171         dar = Signal(64)
 172
 173         # busy/done signals
 174         busy = Signal()
 175         done = Signal()
 176         m.d.comb += self.n.valid_o.eq(busy & done)
 177         m.d.comb += self.p.ready_o.eq(~busy)
 178
 179         # take copy of X-Form SPR field
 180         x_fields = self.fields.FormXFX
 181         spr = Signal(len(x_fields.SPR))
 182         comb += spr.eq(decode_spr_num(x_fields.SPR))
 183
 184         # ok so we have to "pulse" the MMU (or dcache) rather than
 185         # hold the valid hi permanently.  guess what this does...
 186         valid = Signal()
 187         blip = Signal()
 188         m.d.comb += blip.eq(rising_edge(m, valid))
 189
 190         with m.If(~busy):
 191             with m.If(self.p.valid_i):
 192                 m.d.sync += busy.eq(1)
 193         with m.Else():
 194
 195             # based on the Micro-Op, we work out which of MMU or DCache
 196             # should "action" the operation.  one of MMU or DCache gets
 197             # enabled ("valid") and we twiddle our thumbs until it
 198             # responds ("done").
 199
 200             # FIXME: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
 201
 202             with m.Switch(op.insn_type):
 203                 comb += self.debug0.eq(3)
 204                 with m.Case(MicrOp.OP_MTSPR):
 205                     # subset SPR: first check a few bits
 206                     with m.If(~spr[9] & ~spr[5]):
 207                         with m.If(spr[0]):
 208                             comb += dsisr.eq(a_i[:32])
 209                         with m.Else():
 210                             comb += dar.eq(a_i)
 211                         comb += done.eq(1)
 212                     # pass it over to the MMU instead
 213                     with m.Else():
 214                         # blip the MMU and wait for it to complete
 215                         comb += valid.eq(1)   # start "pulse"
 216                         comb += l_in.valid.eq(blip)   # start
 217                         comb += l_in.mtspr.eq(1)      # mtspr mode
 218                         comb += l_in.sprn.eq(spr)  # which SPR
 219                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 220                         comb += done.eq(l_out.done) # zzzz
 221
 222                 with m.Case(MicrOp.OP_MFSPR):
 223                     comb += self.debug0.eq(3)
 224                     # subset SPR: first check a few bits
 225                     with m.If(~spr[9] & ~spr[5]):
 226                         with m.If(spr[0]):
 227                             comb += o.data.eq(dsisr)
 228                         with m.Else():
 229                             comb += o.data.eq(dar)
 230                         comb += o.ok.eq(1)
 231                         comb += done.eq(1)
 232                     # pass it over to the MMU instead
 233                     with m.Else():
 234                         # blip the MMU and wait for it to complete
 235                         comb += valid.eq(1)   # start "pulse"
 236                         comb += l_in.valid.eq(blip)   # start
 237                         comb += l_in.mtspr.eq(0)   # mfspr!=mtspr
 238                         comb += l_in.sprn.eq(spr)  # which SPR
 239                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 240                         comb += o.data.eq(l_out.sprval) # SPR from MMU
 241                         comb += o.ok.eq(l_out.done) # only when l_out valid
 242                         comb += done.eq(l_out.done) # zzzz
 243
 244                 with m.Case(MicrOp.OP_DCBZ):
 245                     # activate dcbz mode (spec: v3.0B p850)
 246                     comb += valid.eq(1)   # start "pulse"
 247                     comb += d_in.valid.eq(blip)     # start
 248                     comb += d_in.dcbz.eq(1)         # dcbz mode
 249                     comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
 250                     comb += done.eq(d_out.store_done)     # TODO
 251                     comb += self.debug0.eq(1)
 252
 253                 with m.Case(MicrOp.OP_TLBIE):
 254                     # pass TLBIE request to MMU (spec: v3.0B p1034)
 255                     # note that the spr is *not* an actual spr number, it's
 256                     # just that those bits happen to match with field bits
 257                     # RIC, PRS, R
 258                     comb += valid.eq(1)   # start "pulse"
 259                     comb += l_in.valid.eq(blip)   # start
 260                     comb += l_in.tlbie.eq(1)   # mtspr mode
 261                     comb += l_in.sprn.eq(spr)  # use sprn to send insn bits
 262                     comb += l_in.addr.eq(b_i)  # incoming operand (RB)
 263                     comb += done.eq(l_out.done) # zzzz
 264                     comb += self.debug0.eq(2)
 265
 266             with m.If(self.n.ready_i & self.n.valid_o):
 267                 m.d.sync += busy.eq(0)
 268
 269         return m
 270
 271     def __iter__(self):
 272         yield from self.p
 273         yield from self.n
 274
 275     def ports(self):
 276         return list(self)