src/soc/fu/mmu/fsm.py

   1 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
   2 from nmigen import Const
   3 from soc.fu.mmu.pipe_data import MMUInputData, MMUOutputData, MMUPipeSpec
   4 from nmutil.singlepipe import ControlBase
   5 from nmutil.util import rising_edge
   6
   7 from soc.experiment.mmu import MMU
   8 from soc.experiment.dcache import DCache
   9
  10 from soc.decoder.power_fields import DecodeFields
  11 from soc.decoder.power_fieldsn import SignalBitRange
  12 from soc.decoder.power_decoder2 import decode_spr_num
  13 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
  14
  15 from soc.experiment.pimem import PortInterface
  16 from soc.experiment.pimem import PortInterfaceBase
  17
  18 from soc.experiment.mem_types import LoadStore1ToDCacheType, LoadStore1ToMMUType
  19 from soc.experiment.mem_types import DCacheToLoadStore1Type, MMUToLoadStore1Type
  20
  21 # for testing purposes
  22 from soc.experiment.testmem import TestMemory
  23
  24 # glue logic for microwatt mmu and dcache
  25 class LoadStore1(PortInterfaceBase):
  26     def __init__(self, regwid=64, addrwid=4):
  27         super().__init__(regwid, addrwid)
  28         self.d_in  = LoadStore1ToDCacheType()
  29         self.d_out = DCacheToLoadStore1Type()
  30         self.l_in  = LoadStore1ToMMUType()
  31         self.l_out = MMUToLoadStore1Type()
  32         # for debugging with gtkwave only
  33         self.debug1 = Signal()
  34         self.debug2 = Signal()
  35
  36     def set_wr_addr(self, m, addr, mask):
  37         m.d.comb += self.d_in.addr.eq(addr)
  38         m.d.comb += self.l_in.addr.eq(addr)
  39         # TODO set mask
  40         return None
  41
  42     def set_rd_addr(self, m, addr, mask):
  43         m.d.comb += self.d_in.addr.eq(addr)
  44         m.d.comb += self.l_in.addr.eq(addr)
  45         m.d.comb += self.debug1.eq(1)
  46         # TODO set mask
  47         return None
  48
  49     def set_wr_data(self, m, data, wen):
  50         m.d.comb += self.d_in.data.eq(data)
  51         # TODO set wen
  52         st_ok = Const(1, 1)
  53         return st_ok
  54
  55     def get_rd_data(self, m):
  56         ld_ok = Const(1, 1)
  57         m.d.comb += self.debug2.eq(1)           #const high
  58         data = self.d_out.data
  59         return data, ld_ok
  60
  61     def elaborate(self, platform):
  62         m = super().elaborate(platform)
  63         #TODO
  64
  65         return m
  66
  67     def ports(self):
  68         yield from super().ports()
  69         # TODO: memory ports
  70
  71 class FSMMMUStage(ControlBase):
  72     def __init__(self, pspec):
  73         super().__init__()
  74         self.pspec = pspec
  75
  76         # set up p/n data
  77         self.p.data_i = MMUInputData(pspec)
  78         self.n.data_o = MMUOutputData(pspec)
  79
  80         # incoming PortInterface
  81         self.ldst = LoadStore1()       # TODO make this depend on pspec
  82         self.pi = self.ldst.pi
  83
  84         # this Function Unit is extremely unusual in that it actually stores a
  85         # "thing" rather than "processes inputs and produces outputs".  hence
  86         # why it has to be a FSM.  linking up LD/ST however is going to have
  87         # to be done back in Issuer (or Core)
  88
  89         self.mmu = MMU()
  90         self.dcache = DCache()
  91         regwid=64
  92         aw = 5
  93         # for verification of DCache
  94         # XXX -- read testmem.py
  95         self.testmem = TestMemory(regwid, aw, granularity=regwid//8, init=False)
  96
  97         # make life a bit easier in Core
  98         self.pspec.mmu = self.mmu
  99         self.pspec.dcache = self.dcache
 100
 101         # debugging output for gtkw
 102         self.debug0 = Signal(4)
 103         self.debug_wb_cyc = Signal()
 104         self.debug_wb_stb = Signal()
 105         self.debug_wb_we = Signal()
 106         #self.debug1 = Signal(64)
 107         #self.debug2 = Signal(64)
 108         #self.debug3 = Signal(64)
 109
 110         # for SPR field number access
 111         i = self.p.data_i
 112         self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
 113         self.fields.create_specs()
 114
 115     def elaborate(self, platform):
 116         m = super().elaborate(platform)
 117         comb = m.d.comb
 118
 119         # link mmu and dcache together
 120         m.submodules.dcache = dcache = self.dcache
 121         m.submodules.mmu = mmu = self.mmu
 122         m.submodules.ldst = ldst = self.ldst
 123         m.submodules.testmem = testmem = self.testmem
 124         m.d.comb += dcache.m_in.eq(mmu.d_out)
 125         m.d.comb += mmu.d_in.eq(dcache.m_out)
 126         l_in, l_out = mmu.l_in, mmu.l_out
 127         d_in, d_out = dcache.d_in, dcache.d_out
 128
 129         # link ldst and dcache together
 130         comb += l_in.eq(self.ldst.l_in)
 131         comb += self.ldst.l_out.eq(l_out)
 132         comb += d_in.eq(self.ldst.d_in)
 133         comb += self.ldst.d_out.eq(self.dcache.d_out)
 134
 135         # [TODO] connect DCache wishbone (wb_out,wb_in) to testmemory
 136
 137         # connect DCache wishbone master to debugger
 138         comb += self.debug_wb_cyc.eq(dcache.wb_out.cyc)
 139         comb += self.debug_wb_stb.eq(dcache.wb_out.stb)
 140         comb += self.debug_wb_we.eq(dcache.wb_out.we)
 141
 142         data_i, data_o = self.p.data_i, self.n.data_o
 143         a_i, b_i, o = data_i.ra, data_i.rb, data_o.o
 144         op = data_i.ctx.op
 145
 146         # TODO: link these SPRs somewhere
 147         dsisr = Signal(64)
 148         dar = Signal(64)
 149
 150         # busy/done signals
 151         busy = Signal()
 152         done = Signal()
 153         m.d.comb += self.n.valid_o.eq(busy & done)
 154         m.d.comb += self.p.ready_o.eq(~busy)
 155
 156         # take copy of X-Form SPR field
 157         x_fields = self.fields.FormXFX
 158         spr = Signal(len(x_fields.SPR))
 159         comb += spr.eq(decode_spr_num(x_fields.SPR))
 160
 161         # ok so we have to "pulse" the MMU (or dcache) rather than
 162         # hold the valid hi permanently.  guess what this does...
 163         valid = Signal()
 164         blip = Signal()
 165         m.d.comb += blip.eq(rising_edge(m, valid))
 166
 167         with m.If(~busy):
 168             with m.If(self.p.valid_i):
 169                 m.d.sync += busy.eq(1)
 170         with m.Else():
 171
 172             # based on the Micro-Op, we work out which of MMU or DCache
 173             # should "action" the operation.  one of MMU or DCache gets
 174             # enabled ("valid") and we twiddle our thumbs until it
 175             # responds ("done").
 176
 177             # FIXME: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
 178
 179             with m.Switch(op.insn_type):
 180                 comb += self.debug0.eq(3)
 181                 with m.Case(MicrOp.OP_MTSPR):
 182                     # subset SPR: first check a few bits
 183                     with m.If(~spr[9] & ~spr[5]):
 184                         with m.If(spr[0]):
 185                             comb += dsisr.eq(a_i[:32])
 186                         with m.Else():
 187                             comb += dar.eq(a_i)
 188                         comb += done.eq(1)
 189                     # pass it over to the MMU instead
 190                     with m.Else():
 191                         # blip the MMU and wait for it to complete
 192                         comb += valid.eq(1)   # start "pulse"
 193                         comb += l_in.valid.eq(blip)   # start
 194                         comb += l_in.mtspr.eq(1)      # mtspr mode
 195                         comb += l_in.sprn.eq(spr)  # which SPR
 196                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 197                         comb += done.eq(l_out.done) # zzzz
 198
 199                 with m.Case(MicrOp.OP_MFSPR):
 200                     comb += self.debug0.eq(3)
 201                     # subset SPR: first check a few bits
 202                     with m.If(~spr[9] & ~spr[5]):
 203                         with m.If(spr[0]):
 204                             comb += o.data.eq(dsisr)
 205                         with m.Else():
 206                             comb += o.data.eq(dar)
 207                         comb += o.ok.eq(1)
 208                         comb += done.eq(1)
 209                     # pass it over to the MMU instead
 210                     with m.Else():
 211                         # blip the MMU and wait for it to complete
 212                         comb += valid.eq(1)   # start "pulse"
 213                         comb += l_in.valid.eq(blip)   # start
 214                         comb += l_in.mtspr.eq(0)   # mfspr!=mtspr
 215                         comb += l_in.sprn.eq(spr)  # which SPR
 216                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 217                         comb += o.data.eq(l_out.sprval) # SPR from MMU
 218                         comb += o.ok.eq(l_out.done) # only when l_out valid
 219                         comb += done.eq(l_out.done) # zzzz
 220
 221                 with m.Case(MicrOp.OP_DCBZ):
 222                     # activate dcbz mode (spec: v3.0B p850)
 223                     comb += valid.eq(1)   # start "pulse"
 224                     comb += d_in.valid.eq(blip)     # start
 225                     comb += d_in.dcbz.eq(1)         # dcbz mode
 226                     comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
 227                     comb += done.eq(d_out.store_done)     # TODO
 228                     comb += self.debug0.eq(1)
 229
 230                 with m.Case(MicrOp.OP_TLBIE):
 231                     # pass TLBIE request to MMU (spec: v3.0B p1034)
 232                     # note that the spr is *not* an actual spr number, it's
 233                     # just that those bits happen to match with field bits
 234                     # RIC, PRS, R
 235                     comb += valid.eq(1)   # start "pulse"
 236                     comb += l_in.valid.eq(blip)   # start
 237                     comb += l_in.tlbie.eq(1)   # mtspr mode
 238                     comb += l_in.sprn.eq(spr)  # use sprn to send insn bits
 239                     comb += l_in.addr.eq(b_i)  # incoming operand (RB)
 240                     comb += done.eq(l_out.done) # zzzz
 241                     comb += self.debug0.eq(2)
 242
 243             with m.If(self.n.ready_i & self.n.valid_o):
 244                 m.d.sync += busy.eq(0)
 245
 246         return m
 247
 248     def __iter__(self):
 249         yield from self.p
 250         yield from self.n
 251
 252     def ports(self):
 253         return list(self)