src/soc/fu/mmu/fsm.py

   1 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
   2 from soc.fu.mmu.pipe_data import MMUInputData, MMUOutputData, MMUPipeSpec
   3 from nmutil.singlepipe import ControlBase
   4
   5
   6 class FSMMMUStage(ControlBase):
   7     def __init__(self, pspec):
   8         super().__init__()
   9         self.pspec = pspec
  10         # set up p/n data
  11         self.p.data_i = MMUInputData(pspec)
  12         self.n.data_o = MMUOutputData(pspec)
  13
  14     def elaborate(self, platform):
  15         m = super().elaborate(platform)
  16         data_i = self.p.data_i
  17         data_o = self.n.data_o
  18
  19         m.d.comb += self.n.valid_o.eq(~self.empty & self.div_state_next.o.done)
  20         m.d.comb += self.p.ready_o.eq(self.empty)
  21         m.d.sync += self.saved_state.eq(self.div_state_next.o)
  22
  23         with m.If(self.empty):
  24             with m.If(self.p.valid_i):
  25                 m.d.sync += self.empty.eq(0)
  26                 m.d.sync += self.saved_input_data.eq(data_i)
  27         with m.Else():
  28             m.d.comb += [
  29             with m.If(self.n.ready_i & self.n.valid_o):
  30                 m.d.sync += self.empty.eq(1)
  31
  32         return m
  33
  34     def __iter__(self):
  35         yield from self.p
  36         yield from self.n
  37
  38     def ports(self):
  39         return list(self)