1 from nmigen
import Elaboratable
, Module
, Signal
, Shape
, unsigned
, Cat
, Mux
2 from nmigen
import Const
3 from soc
.fu
.mmu
.pipe_data
import MMUInputData
, MMUOutputData
, MMUPipeSpec
4 from nmutil
.singlepipe
import ControlBase
5 from nmutil
.util
import rising_edge
7 from soc
.experiment
.mmu
import MMU
8 from soc
.experiment
.dcache
import DCache
10 from soc
.decoder
.power_fields
import DecodeFields
11 from soc
.decoder
.power_fieldsn
import SignalBitRange
12 from soc
.decoder
.power_decoder2
import decode_spr_num
13 from soc
.decoder
.power_enums
import MicrOp
, SPR
, XER_bits
15 from soc
.experiment
.pimem
import PortInterface
16 from soc
.experiment
.pimem
import PortInterfaceBase
18 from soc
.experiment
.mem_types
import LoadStore1ToDCacheType
, LoadStore1ToMMUType
19 from soc
.experiment
.mem_types
import DCacheToLoadStore1Type
, MMUToLoadStore1Type
22 # glue logic for microwatt mmu and dcache
23 class LoadStore1(PortInterfaceBase
):
24 def __init__(self
, regwid
=64, addrwid
=4):
25 super().__init
__(regwid
, addrwid
)
26 self
.d_in
= LoadStore1ToDCacheType()
27 self
.d_out
= DCacheToLoadStore1Type()
28 self
.l_in
= LoadStore1ToMMUType()
29 self
.l_out
= MMUToLoadStore1Type()
30 # for debugging with gtkwave only
31 self
.debug1
= Signal()
32 self
.debug2
= Signal()
34 self
.mmureq
= Signal()
35 self
.derror
= Signal()
37 def set_wr_addr(self
, m
, addr
, mask
):
38 #m.d.comb += self.d_in.valid.eq(1)
39 #m.d.comb += self.l_in.valid.eq(1)
40 #m.d.comb += self.d_in.load.eq(0)
41 #m.d.comb += self.l_in.load.eq(0)
42 # set phys addr on both units
43 m
.d
.comb
+= self
.d_in
.addr
.eq(addr
)
44 m
.d
.comb
+= self
.l_in
.addr
.eq(addr
)
48 def set_rd_addr(self
, m
, addr
, mask
):
49 m
.d
.comb
+= self
.d_in
.valid
.eq(1)
50 m
.d
.comb
+= self
.l_in
.valid
.eq(1)
51 m
.d
.comb
+= self
.d_in
.load
.eq(1)
52 m
.d
.comb
+= self
.l_in
.load
.eq(1)
53 m
.d
.comb
+= self
.d_in
.addr
.eq(addr
)
54 m
.d
.comb
+= self
.l_in
.addr
.eq(addr
)
55 m
.d
.comb
+= self
.debug1
.eq(1)
56 # m.d.comb += self.debug2.eq(1)
57 return None #FIXME return value
59 def set_wr_data(self
, m
, data
, wen
):
60 m
.d
.comb
+= self
.d_in
.data
.eq(data
)
65 def get_rd_data(self
, m
):
67 data
= self
.d_out
.data
71 if d_in.error = '1' then
72 if d_in.cache_paradox = '1' then
73 -- signal an interrupt straight away
75 dsisr(63 - 38) := not r2.req.load;
76 -- XXX there is no architected bit for this
77 -- (probably should be a machine check in fact)
78 dsisr(63 - 35) := d_in.cache_paradox;
80 -- Look up the translation for TLB miss
81 -- and also for permission error and RC error
82 -- in case the PTE has been updated.
84 v.state := MMU_LOOKUP;
90 def elaborate(self
, platform
):
91 m
= super().elaborate(platform
)
96 with m
.If(d_out
.error
):
97 with m
.If(d_out
.cache_paradox
):
98 m
.d
.comb
+= self
.derror
.eq(1)
99 # dsisr(63 - 38) := not r2.req.load;
100 # -- XXX there is no architected bit for this
101 # -- (probably should be a machine check in fact)
102 # dsisr(63 - 35) := d_in.cache_paradox;
104 # Look up the translation for TLB miss
105 # and also for permission error and RC error
106 # in case the PTE has been updated.
107 m
.d
.comb
+= self
.mmureq
.eq(1)
108 # v.state := MMU_LOOKUP;
109 # v.stage1_en := '0';
111 exc
= self
.pi
.exception_o
113 #happened, alignment, instr_fault, invalid,
114 m
.d
.comb
+= exc
.happened
.eq(d_out
.error | l_out
.err
)
115 m
.d
.comb
+= exc
.invalid
.eq(l_out
.invalid
)
117 #badtree, perm_error, rc_error, segment_fault
118 m
.d
.comb
+= exc
.badtree
.eq(l_out
.badtree
)
119 m
.d
.comb
+= exc
.perm_error
.eq(l_out
.perm_error
)
120 m
.d
.comb
+= exc
.rc_error
.eq(l_out
.rc_error
)
121 m
.d
.comb
+= exc
.segment_fault
.eq(l_out
.segerr
)
123 # TODO connect those signals somewhere
124 #print(d_out.valid) -> no error
125 #print(d_out.store_done) -> no error
126 #print(d_out.cache_paradox) -> ?
127 #print(l_out.done) -> no error
129 # TODO some exceptions set SPRs
134 yield from super().ports()
137 class FSMMMUStage(ControlBase
):
138 def __init__(self
, pspec
):
143 self
.p
.data_i
= MMUInputData(pspec
)
144 self
.n
.data_o
= MMUOutputData(pspec
)
146 # incoming PortInterface
147 self
.ldst
= LoadStore1() # TODO make this depend on pspec
148 self
.pi
= self
.ldst
.pi
150 # this Function Unit is extremely unusual in that it actually stores a
151 # "thing" rather than "processes inputs and produces outputs". hence
152 # why it has to be a FSM. linking up LD/ST however is going to have
153 # to be done back in Issuer (or Core)
156 self
.dcache
= DCache()
158 # make life a bit easier in Core
159 self
.pspec
.mmu
= self
.mmu
160 self
.pspec
.dcache
= self
.dcache
162 # debugging output for gtkw
163 self
.debug0
= Signal(4)
164 self
.debug1
= Signal()
165 #self.debug2 = Signal(64)
166 #self.debug3 = Signal(64)
167 self
.illegal
= Signal()
169 # for SPR field number access
171 self
.fields
= DecodeFields(SignalBitRange
, [i
.ctx
.op
.insn
])
172 self
.fields
.create_specs()
174 def elaborate(self
, platform
):
175 m
= super().elaborate(platform
)
178 # link mmu and dcache together
179 m
.submodules
.dcache
= dcache
= self
.dcache
180 m
.submodules
.mmu
= mmu
= self
.mmu
181 m
.submodules
.ldst
= ldst
= self
.ldst
182 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
)
183 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
)
184 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
185 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
186 wb_out
, wb_in
= dcache
.wb_out
, dcache
.wb_in
188 # link ldst and dcache together
189 comb
+= l_in
.eq(self
.ldst
.l_in
)
190 comb
+= self
.ldst
.l_out
.eq(l_out
)
191 comb
+= d_in
.eq(self
.ldst
.d_in
)
192 comb
+= self
.ldst
.d_out
.eq(self
.dcache
.d_out
)
194 data_i
, data_o
= self
.p
.data_i
, self
.n
.data_o
195 a_i
, b_i
, o
, spr1_o
= data_i
.ra
, data_i
.rb
, data_o
.o
, data_o
.spr1
198 # TODO: link these SPRs somewhere
205 m
.d
.comb
+= self
.n
.valid_o
.eq(busy
& done
)
206 m
.d
.comb
+= self
.p
.ready_o
.eq(~busy
)
208 # take copy of X-Form SPR field
209 x_fields
= self
.fields
.FormXFX
210 spr
= Signal(len(x_fields
.SPR
))
211 comb
+= spr
.eq(decode_spr_num(x_fields
.SPR
))
213 # ok so we have to "pulse" the MMU (or dcache) rather than
214 # hold the valid hi permanently. guess what this does...
217 m
.d
.comb
+= blip
.eq(rising_edge(m
, valid
))
220 with m
.If(self
.p
.valid_i
):
221 m
.d
.sync
+= busy
.eq(1)
224 # based on the Micro-Op, we work out which of MMU or DCache
225 # should "action" the operation. one of MMU or DCache gets
226 # enabled ("valid") and we twiddle our thumbs until it
229 # FIXME: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
231 with m
.Switch(op
.insn_type
):
232 with m
.Case(MicrOp
.OP_MTSPR
):
233 # despite redirection this FU **MUST** behave exactly
234 # like the SPR FU. this **INCLUDES** updating the SPR
235 # regfile because the CSV file entry for OP_MTSPR
236 # categorically defines and requires the expectation
237 # that the CompUnit **WILL** write to the regfile.
238 comb
+= spr1_o
.data
.eq(spr
)
239 comb
+= spr1_o
.ok
.eq(1)
240 # subset SPR: first check a few bits
241 with m
.If(~spr
[9] & ~spr
[5]):
242 comb
+= self
.debug0
.eq(3)
244 comb
+= dsisr
.eq(a_i
[:32])
248 # pass it over to the MMU instead
250 comb
+= self
.debug0
.eq(4)
251 # blip the MMU and wait for it to complete
252 comb
+= valid
.eq(1) # start "pulse"
253 comb
+= l_in
.valid
.eq(blip
) # start
254 comb
+= l_in
.mtspr
.eq(1) # mtspr mode
255 comb
+= l_in
.sprn
.eq(spr
) # which SPR
256 comb
+= l_in
.rs
.eq(a_i
) # incoming operand (RS)
257 comb
+= done
.eq(1) # FIXME l_out.done
259 with m
.Case(MicrOp
.OP_MFSPR
):
260 # subset SPR: first check a few bits
261 with m
.If(~spr
[9] & ~spr
[5]):
262 comb
+= self
.debug0
.eq(5)
264 comb
+= o
.data
.eq(dsisr
)
266 comb
+= o
.data
.eq(dar
)
269 # pass it over to the MMU instead
271 comb
+= self
.debug0
.eq(6)
272 # blip the MMU and wait for it to complete
273 comb
+= valid
.eq(1) # start "pulse"
274 comb
+= l_in
.valid
.eq(blip
) # start
275 comb
+= l_in
.mtspr
.eq(0) # mfspr!=mtspr
276 comb
+= l_in
.sprn
.eq(spr
) # which SPR
277 comb
+= l_in
.rs
.eq(a_i
) # incoming operand (RS)
278 comb
+= o
.data
.eq(l_out
.sprval
) # SPR from MMU
279 comb
+= o
.ok
.eq(l_out
.done
) # only when l_out valid
280 comb
+= done
.eq(1) # FIXME l_out.done
282 with m
.Case(MicrOp
.OP_DCBZ
):
283 # activate dcbz mode (spec: v3.0B p850)
284 comb
+= valid
.eq(1) # start "pulse"
285 comb
+= d_in
.valid
.eq(blip
) # start
286 comb
+= d_in
.dcbz
.eq(1) # dcbz mode
287 comb
+= d_in
.addr
.eq(a_i
+ b_i
) # addr is (RA|0) + RB
288 comb
+= done
.eq(d_out
.store_done
) # TODO
289 comb
+= self
.debug0
.eq(1)
291 with m
.Case(MicrOp
.OP_TLBIE
):
292 # pass TLBIE request to MMU (spec: v3.0B p1034)
293 # note that the spr is *not* an actual spr number, it's
294 # just that those bits happen to match with field bits
296 comb
+= valid
.eq(1) # start "pulse"
297 comb
+= l_in
.valid
.eq(blip
) # start
298 comb
+= l_in
.tlbie
.eq(1) # mtspr mode
299 comb
+= l_in
.sprn
.eq(spr
) # use sprn to send insn bits
300 comb
+= l_in
.addr
.eq(b_i
) # incoming operand (RB)
301 comb
+= done
.eq(l_out
.done
) # zzzz
302 comb
+= self
.debug0
.eq(2)
303 with m
.Case(MicrOp
.OP_ILLEGAL
):
304 comb
+= self
.illegal
.eq(1)
306 with m
.If(self
.n
.ready_i
& self
.n
.valid_o
):
307 m
.d
.sync
+= busy
.eq(0)