2 Based on microwatt mmu.vhdl
4 * https://bugs.libre-soc.org/show_bug.cgi?id=491
5 * https://bugs.libre-soc.org/show_bug.cgi?id=450
8 from nmigen
import Elaboratable
, Module
, Signal
, Shape
, unsigned
, Cat
, Mux
9 from nmigen
import Record
, Memory
10 from nmigen
import Const
11 from soc
.fu
.mmu
.pipe_data
import MMUInputData
, MMUOutputData
, MMUPipeSpec
12 from nmutil
.singlepipe
import ControlBase
13 from nmutil
.util
import rising_edge
15 from soc
.experiment
.mmu
import MMU
17 from openpower
.consts
import MSR
18 from openpower
.decoder
.power_fields
import DecodeFields
19 from openpower
.decoder
.power_fieldsn
import SignalBitRange
20 from openpower
.decoder
.power_decoder2
import decode_spr_num
21 from openpower
.decoder
.power_enums
import MicrOp
23 from soc
.experiment
.mem_types
import LoadStore1ToMMUType
24 from soc
.experiment
.mem_types
import MMUToLoadStore1Type
26 from soc
.fu
.ldst
.loadstore
import LoadStore1
, TestSRAMLoadStore1
27 from nmutil
.util
import Display
29 class FSMMMUStage(ControlBase
):
32 FSM-based MMU: must call set_ldst_interface and pass in an instance
33 of a LoadStore1. this to comply with the ConfigMemoryPortInterface API
35 this Function Unit is extremely unusual in that it actually stores a
36 "thing" rather than "processes inputs and produces outputs". hence
37 why it has to be a FSM. linking up LD/ST however is going to have
38 to be done back in Issuer (or Core). sorted: call set_ldst_interface
40 def __init__(self
, pspec
):
45 self
.p
.i_data
= MMUInputData(pspec
)
46 self
.n
.o_data
= MMUOutputData(pspec
)
50 # debugging output for gtkw
51 self
.debug0
= Signal(4)
52 self
.illegal
= Signal()
54 # for SPR field number access
56 self
.fields
= DecodeFields(SignalBitRange
, [i
.ctx
.op
.insn
])
57 self
.fields
.create_specs()
59 def set_ldst_interface(self
, ldst
):
60 """must be called back in Core, after FUs have been set up.
61 one of those will be the MMU (us!) but the LoadStore1 instance
62 must be set up in ConfigMemoryPortInterface. sigh.
64 # incoming PortInterface
66 self
.dcache
= self
.ldst
.dcache
67 self
.pi
= self
.ldst
.pi
69 def elaborate(self
, platform
):
70 assert hasattr(self
, "dcache"), "remember to call set_ldst_interface"
71 m
= super().elaborate(platform
)
72 comb
, sync
= m
.d
.comb
, m
.d
.sync
75 # link mmu and dcache together
76 m
.submodules
.mmu
= mmu
= self
.mmu
77 ldst
= self
.ldst
# managed externally: do not add here
78 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
79 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
81 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
82 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
83 wb_out
, wb_in
= dcache
.wb_out
, dcache
.wb_in
85 # link ldst and MMU together
86 comb
+= l_in
.eq(ldst
.m_out
)
87 comb
+= ldst
.m_in
.eq(l_out
)
89 i_data
, o_data
= self
.p
.i_data
, self
.n
.o_data
90 a_i
, b_i
, o
, spr1_o
= i_data
.ra
, i_data
.rb
, o_data
.o
, o_data
.spr1
95 # these are set / got here *ON BEHALF* of LoadStore1
96 # XXX have to deal with this another way
97 # dsisr, dar = ldst.dsisr, ldst.dar
102 m
.d
.comb
+= self
.n
.o_valid
.eq(busy
& done
)
103 m
.d
.comb
+= self
.p
.o_ready
.eq(~busy
)
105 # take copy of X-Form SPR field
106 x_fields
= self
.fields
.FormXFX
107 spr
= Signal(len(x_fields
.SPR
))
108 comb
+= spr
.eq(decode_spr_num(x_fields
.SPR
))
110 # based on MSR bits, set priv and virt mode. TODO: 32-bit mode
111 # XXX WARK-WARK, this should be done in loadstore.py
112 # (through the PortInterface)
113 #comb += d_in.priv_mode.eq(~msr_i[MSR.PR])
114 #comb += d_in.virt_mode.eq(msr_i[MSR.DR])
115 #comb += d_in.mode_32bit.eq(msr_i[MSR.SF]) # ?? err
117 # ok so we have to "pulse" the MMU (or dcache) rather than
118 # hold the valid hi permanently. guess what this does...
121 m
.d
.comb
+= blip
.eq(rising_edge(m
, valid
))
124 with m
.If(self
.p
.i_valid
):
128 # based on the Micro-Op, we work out which of MMU or DCache
129 # should "action" the operation. one of MMU or DCache gets
130 # enabled ("valid") and we twiddle our thumbs until it
133 # WIP: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
135 with m
.Switch(op
.insn_type
):
136 with m
.Case(MicrOp
.OP_MTSPR
):
137 comb
+= Display("MMUTEST: OP_MTSPR: spr=%i", spr
)
138 # despite redirection this FU **MUST** behave exactly
139 # like the SPR FU. this **INCLUDES** updating the SPR
140 # regfile because the CSV file entry for OP_MTSPR
141 # categorically defines and requires the expectation
142 # that the CompUnit **WILL** write to the regfile.
143 comb
+= spr1_o
.data
.eq(a_i
)
144 comb
+= spr1_o
.ok
.eq(1)
145 # subset SPR: first check a few bits
146 # XXX NOTE this must now cover **FOUR** values: this
147 # test might not be adequate. DSISR, DAR, PGTBL and PID
148 # must ALL be covered here.
149 with m
.If(~spr
[9] & ~spr
[5]):
150 comb
+= self
.debug0
.eq(3)
151 #if matched update local cached value
152 #commented out because there is a driver conflict
154 # sync += dsisr.eq(a_i[:32])
156 # sync += dar.eq(a_i)
158 # pass it over to the MMU instead
161 comb
+= self
.debug0
.eq(4)
162 # blip the MMU and wait for it to complete
163 comb
+= valid
.eq(1) # start "pulse"
164 comb
+= l_in
.valid
.eq(blip
) # start
165 comb
+= l_in
.mtspr
.eq(1) # mtspr mode
166 comb
+= l_in
.sprn
.eq(spr
) # which SPR
167 comb
+= l_in
.rs
.eq(a_i
) # incoming operand (RS)
168 comb
+= done
.eq(1) # FIXME l_out.done
170 with m
.Case(MicrOp
.OP_MFSPR
):
171 comb
+= Display("MMUTEST: OP_MFSPR: spr=%i returns=%i",
173 comb
+= o
.data
.eq(spr1_i
)
177 with m
.Case(MicrOp
.OP_TLBIE
):
178 comb
+= Display("MMUTEST: OP_TLBIE: insn_bits=%i", spr
)
179 # pass TLBIE request to MMU (spec: v3.0B p1034)
180 # note that the spr is *not* an actual spr number, it's
181 # just that those bits happen to match with field bits
183 comb
+= Display("TLBIE: %i %i", spr
, l_out
.done
)
184 comb
+= valid
.eq(1) # start "pulse"
185 comb
+= l_in
.valid
.eq(blip
) # start
186 comb
+= l_in
.tlbie
.eq(1) # mtspr mode
187 comb
+= l_in
.sprn
.eq(spr
) # use sprn to send insn bits
188 comb
+= l_in
.addr
.eq(b_i
) # incoming operand (RB)
189 comb
+= done
.eq(l_out
.done
) # zzzz
190 comb
+= self
.debug0
.eq(2)
192 with m
.Case(MicrOp
.OP_ILLEGAL
):
193 comb
+= self
.illegal
.eq(1)
195 with m
.If(self
.n
.i_ready
& self
.n
.o_valid
):