src/soc/fu/mmu/fsm.py

   1 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
   2 from nmigen import Const
   3 from soc.fu.mmu.pipe_data import MMUInputData, MMUOutputData, MMUPipeSpec
   4 from nmutil.singlepipe import ControlBase
   5 from nmutil.util import rising_edge
   6
   7 from soc.experiment.mmu import MMU
   8 from soc.experiment.dcache import DCache
   9
  10 from soc.decoder.power_fields import DecodeFields
  11 from soc.decoder.power_fieldsn import SignalBitRange
  12 from soc.decoder.power_decoder2 import decode_spr_num
  13 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
  14
  15 from soc.experiment.pimem import PortInterface
  16 from soc.experiment.pimem import PortInterfaceBase
  17
  18 from soc.experiment.mem_types import LoadStore1ToDCacheType, LoadStore1ToMMUType
  19 from soc.experiment.mem_types import DCacheToLoadStore1Type, MMUToLoadStore1Type
  20
  21 # glue logic for microwatt mmu and dcache
  22 class LoadStore1(PortInterfaceBase):
  23     def __init__(self, regwid=64, addrwid=4):
  24         super().__init__(regwid, addrwid)
  25         self.d_in  = LoadStore1ToDCacheType()
  26         self.d_out = DCacheToLoadStore1Type()
  27         self.l_in  = LoadStore1ToMMUType()
  28         self.l_out = MMUToLoadStore1Type()
  29
  30     def set_wr_addr(self, m, addr, mask):
  31         m.d.comb += self.d_in.addr.eq(addr)
  32         m.d.comb += self.l_in.addr.eq(addr)
  33         # TODO set mask
  34         return None
  35
  36     def set_rd_addr(self, m, addr, mask):
  37         m.d.comb += self.d_in.addr.eq(addr)
  38         m.d.comb += self.l_in.addr.eq(addr)
  39         # TODO set mask
  40         return None
  41
  42     def set_wr_data(self, m, data, wen):
  43         m.d.comb += self.d_in.data.eq(data)
  44         # TODO set wen
  45         st_ok = Const(1, 1)
  46         return st_ok
  47
  48     def get_rd_data(self, m):
  49         ld_ok = Const(1, 1)
  50         data = self.d_out.data
  51         return data, ld_ok
  52
  53     def elaborate(self, platform):
  54         m = super().elaborate(platform)
  55         #TODO
  56
  57         return m
  58
  59     def ports(self):
  60         yield from super().ports()
  61         # TODO: memory ports
  62
  63 class FSMMMUStage(ControlBase):
  64     def __init__(self, pspec):
  65         super().__init__()
  66         self.pspec = pspec
  67
  68         # set up p/n data
  69         self.p.data_i = MMUInputData(pspec)
  70         self.n.data_o = MMUOutputData(pspec)
  71
  72         # incoming PortInterface
  73         self.ldst = LoadStore1()
  74         self.pi = self.ldst.pi
  75
  76         # this Function Unit is extremely unusual in that it actually stores a
  77         # "thing" rather than "processes inputs and produces outputs".  hence
  78         # why it has to be a FSM.  linking up LD/ST however is going to have
  79         # to be done back in Issuer (or Core)
  80
  81         self.mmu = MMU()
  82         self.dcache = DCache()
  83
  84         # make life a bit easier in Core
  85         self.pspec.mmu = self.mmu
  86         self.pspec.dcache = self.dcache
  87
  88         # debugging output for gtkw
  89         self.debug0 = Signal(64)
  90         self.debug1 = Signal(64)
  91         self.debug2 = Signal(64)
  92         self.debug3 = Signal(64)
  93
  94         # for SPR field number access
  95         i = self.p.data_i
  96         self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
  97         self.fields.create_specs()
  98
  99     def elaborate(self, platform):
 100         m = super().elaborate(platform)
 101         comb = m.d.comb
 102
 103         # link mmu and dcache together
 104         m.submodules.dcache = dcache = self.dcache
 105         m.submodules.mmu = mmu = self.mmu
 106         m.submodules.ldst = ldst = self.ldst
 107         m.d.comb += dcache.m_in.eq(mmu.d_out)
 108         m.d.comb += mmu.d_in.eq(dcache.m_out)
 109         l_in, l_out = mmu.l_in, mmu.l_out
 110         d_in, d_out = dcache.d_in, dcache.d_out
 111
 112         comb += l_in.eq(self.ldst.l_in)
 113         comb += self.ldst.l_out.eq(l_out)
 114         comb += d_in.eq(self.ldst.d_in)
 115         comb += self.ldst.d_out.eq(self.dcache.d_out)
 116
 117         data_i, data_o = self.p.data_i, self.n.data_o
 118         a_i, b_i, o = data_i.ra, data_i.rb, data_o.o
 119         op = data_i.ctx.op
 120
 121         # TODO: link these SPRs somewhere
 122         dsisr = Signal(64)
 123         dar = Signal(64)
 124
 125         # busy/done signals
 126         busy = Signal()
 127         done = Signal()
 128         m.d.comb += self.n.valid_o.eq(busy & done)
 129         m.d.comb += self.p.ready_o.eq(~busy)
 130
 131         # take copy of X-Form SPR field
 132         x_fields = self.fields.FormXFX
 133         spr = Signal(len(x_fields.SPR))
 134         comb += spr.eq(decode_spr_num(x_fields.SPR))
 135
 136         # ok so we have to "pulse" the MMU (or dcache) rather than
 137         # hold the valid hi permanently.  guess what this does...
 138         valid = Signal()
 139         blip = Signal()
 140         m.d.comb += blip.eq(rising_edge(m, valid))
 141
 142         with m.If(~busy):
 143             with m.If(self.p.valid_i):
 144                 m.d.sync += busy.eq(1)
 145         with m.Else():
 146
 147             # based on the Micro-Op, we work out which of MMU or DCache
 148             # should "action" the operation.  one of MMU or DCache gets
 149             # enabled ("valid") and we twiddle our thumbs until it
 150             # responds ("done").
 151             with m.Switch(op.insn_type):
 152                 with m.Case(MicrOp.OP_MTSPR):
 153                     comb += self.debug0.eq(0xFF)
 154                     comb += self.debug1.eq(spr)
 155                     comb += self.debug2.eq(a_i)
 156                     comb += self.debug3.eq(a_i[:32])
 157                     # subset SPR: first check a few bits
 158                     with m.If(~spr[9] & ~spr[5]):
 159                         with m.If(spr[0]):
 160                             comb += dsisr.eq(a_i[:32])
 161                         with m.Else():
 162                             comb += dar.eq(a_i)
 163                         comb += done.eq(1)
 164                     # pass it over to the MMU instead
 165                     with m.Else():
 166                         # blip the MMU and wait for it to complete
 167                         comb += valid.eq(1)   # start "pulse"
 168                         comb += l_in.valid.eq(blip)   # start
 169                         comb += l_in.mtspr.eq(1)      # mtspr mode
 170                         comb += l_in.sprn.eq(spr)  # which SPR
 171                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 172                         comb += done.eq(l_out.done) # zzzz
 173
 174                 with m.Case(MicrOp.OP_MFSPR):
 175                     # subset SPR: first check a few bits
 176                     with m.If(~spr[9] & ~spr[5]):
 177                         with m.If(spr[0]):
 178                             comb += o.data.eq(dsisr)
 179                         with m.Else():
 180                             comb += o.data.eq(dar)
 181                         comb += o.ok.eq(1)
 182                         comb += done.eq(1)
 183                     # pass it over to the MMU instead
 184                     with m.Else():
 185                         # blip the MMU and wait for it to complete
 186                         comb += valid.eq(1)   # start "pulse"
 187                         comb += l_in.valid.eq(blip)   # start
 188                         comb += l_in.mtspr.eq(1)   # mtspr mode
 189                         comb += l_in.sprn.eq(spr)  # which SPR
 190                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 191                         comb += o.data.eq(l_out.sprval) # SPR from MMU
 192                         comb += o.ok.eq(l_out.done) # only when l_out valid
 193                         comb += done.eq(l_out.done) # zzzz
 194
 195                 with m.Case(MicrOp.OP_DCBZ):
 196                     # activate dcbz mode (spec: v3.0B p850)
 197                     comb += valid.eq(1)   # start "pulse"
 198                     comb += d_in.valid.eq(blip)     # start
 199                     comb += d_in.dcbz.eq(1)         # dcbz mode
 200                     comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
 201                     comb += done.eq(d_out.store_done)     # TODO
 202
 203                 with m.Case(MicrOp.OP_TLBIE):
 204                     # pass TLBIE request to MMU (spec: v3.0B p1034)
 205                     # note that the spr is *not* an actual spr number, it's
 206                     # just that those bits happen to match with field bits
 207                     # RIC, PRS, R
 208                     comb += valid.eq(1)   # start "pulse"
 209                     comb += l_in.valid.eq(blip)   # start
 210                     comb += l_in.tlbie.eq(1)   # mtspr mode
 211                     comb += l_in.sprn.eq(spr)  # use sprn to send insn bits
 212                     comb += l_in.addr.eq(b_i)  # incoming operand (RB)
 213                     comb += done.eq(l_out.done) # zzzz
 214
 215             with m.If(self.n.ready_i & self.n.valid_o):
 216                 m.d.sync += busy.eq(0)
 217
 218         return m
 219
 220     def __iter__(self):
 221         yield from self.p
 222         yield from self.n
 223
 224     def ports(self):
 225         return list(self)